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| 型号： | DS2790G+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 27/41页 |
| 文件大小： | 0K |
| 描述： | IC FUEL GAUGE BATT 28-TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 燃料，电量检测计/监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TDFN |
| 供应商设备封装： | 28-TDFN-EP（8x4） |
| 包装： | 带卷 (TR) |
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DS2790 Programmable 1-Cell Li-Ion Fuel Gauge and Protector
2-Wire Slave Interrupts
An interrupt is generated when any condition that sets an interrupt status register bit occurs, and the corresponding
interrupt mask bit in the 2-Wire Slave Interrupt Mask Register (TWSIM) is also set. All 2-wire interrupts are
maskable by clearing the corresponding bit in the TWSIM. Upon system reset, all 2-wire interrupt mask bits are
cleared automatically. The interrupt status register is 2 bytes in length and is readable and writeable by the
MAXQ20 core.
Like the high level interrupt status register in the core, when the TWSINT register is read, the state of the interrupt
status bits are returned but not altered. Edge triggered interrupt status bits are cleared by writing a ‘0’ to their
location. Any attempt to write a ‘1’ is ignored. Level triggered interrupt status bits are cleared automatically after the
event that caused the interrupt to occur has ended.
Table 10. 2-Wire Slave Interrupt Sources
INTERRUPT
(TWSINT)
RXD_FULL
RXD_EMPTY
RXD_BYTE
RXD_CMD
TXD_FULL
TXD_EMPTY
TXD_BYTE
MASK
(TWSIM)
RXD_FULL_MASK
RXD_EMPTY
_MASK
RXD_BYTE_MASK
RXD_CMD_MASK
TXD_FULL_MASK
TXD_EMPTY
_MASK
TXD_BYTE_MASK
DESCRIPTION
When the RXD FIFO is full.
RXD buffer is empty.
Byte moved from the incoming shift register to the RXD FIFO.
Command byte receive completed.
TXD buffer is full.
When the TXD FIFO is empty.
Byte moved from TXD FIFO to the outgoing shift register.
TRIGGER
Level
Edge
Edge
Edge
Edge
Level
Edge
A start followed by the address defined in the configuration
START
START_MASK
register was recognized.
Edge
(This bit is not set during a repeated start condition.)
RESTART
_WRITE
RESTART
_READ
STOP
TIMEOUT
RESTART_WRITE
_MASK
RESTART_READ
_MASK
STOP_MASK
TIMEOUT_MASK
A repeated start followed by the address defined in the
configuration register was received with the read/write bit clear.
A repeated start followed by the address defined in the
configuration register was received with the read/write bit set.
After an address qualified Start or Restart, a STOP is recognized
on the bus.
T TIMEOUT or T LOW:SEXT event recognized on the bus. Either timeout
event will reset the TWS interface.
Edge
Edge
Edge
Edge
Transmit and Receive Data Buffers
Since multiple data bytes can be associated with a single command byte, the TWS is designed with transmit and
receive buffers to prevent data loss and reduce CPU overhead during a communication sequence. Data received
from the master is directed to an 8 byte deep receive first in, first out buffer (RXD FIFO) until read by the CPU.
Data to be transmitted by the DS2790 is stored in a separate 8-byte transmit FIFO buffer (TXD FIFO) until the
master reads it. If the RXD FIFO buffer becomes completely full or the TXD FIFO buffer becomes completely
empty during communication, the interface will begin clock extending the bus to maintain data integrity.
The CPU has access to the TXD and RXD FIFOs through the Transmit/Receive Data register (TWSTXD/RXD).
During a master read (TWS transmit) data is pushed onto the TXD FIFO by writing to the TWSTXD/RXD register.
Likewise, during a master write (TWS receive), the CPU can pull data off the RXD FIFO by reading the
TWSTXD/RXD register.
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