- 您现在的位置：买卖IC网 > PDF目录97869 > DS3112 (DALLAS SEMICONDUCTOR) DATACOM, FRAMER, PBGA256 PDF资料下载
参数资料
| 型号： | DS3112 |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封装： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件页数： | 122/134页 |
| 文件大小： | 900K |
| 代理商： | DS3112 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页当前第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页
DS3112
88 of 134
Register Name:
BERTEC0
Register Description:
BERT 24-Bit Error Counter (lower) and Status Information
Register Address:
7Ch
Bit #
765
43210
Name
n/a
RA1
RA0
RLOS
BED
BBCO
BECO
SYNC
Default
---
-----
Bit #
151413
121110
9
8
Name
BEC7
BEC6
BEC5
BEC4
BEC3
BEC2
BEC1
BEC0
Default
000
00000
Note: Bits that are underlined are read only; all other bits are read-write.
Bit 0 / Real Time Synchronization Status (SYNC). Read only real time status of the synchronizer (this
bit is not latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will
be cleared when 6 or more bits out of 64 are received in error.
Bit 1 / BERT Error Counter Overflow (BECO). A latched read only event status bit which is set when
the 24-bit BERT Error Counter (BEC) saturates. Cleared when read and will not be set again until
another overflow occurs (i.e. the BEC counter must be cleared and allowed to overflow again). The
setting of this status bit can cause a hardware interrupt to occur if the IEOF bit in BERT Control Register
0 is set to a one and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read. See Figure 8.2A.
Bit 2 / BERT Bit Counter Overflow (BBCO). A latched read only event status bit which is set when
the 32-bit BERT Bit Counter (BBC) saturates. Cleared when read and will not be set again until another
overflow occurs (i.e. the BBC counter must be cleared and allowed to overflow again). The setting of
this status bit can cause a hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to
a one and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will
be allowed to clear when this bit is read. See Figure 8.2A.
Bit 3 / Bit Error Detected (BED). A latched read only event status bit which is set when a bit error is
detected. The receive BERT must be in synchronization for it to detect bit errors. This bit will be cleared
when read. The setting of this status bit can cause a hardware interrupt to occur if the IEBED bit in BERT
Control Register 0 is set to a one and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set
to a one. The interrupt will be allowed to clear when this bit is read. See Figure 8.2A.
Bit 4 / Receive Loss Of Synchronization (RLOS). A latched read only alarm status bit which is set
whenever the receive BERT begins searching for a pattern. Once synchronization is achieved, this bit
will remain set until read. A change in this status bit (i.e. the synchronizer goes into or out of
synchronization) can cause a hardware interrupt to occur if the IESYNC bit in BERT Control Register 0
is set to a one and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read. See Figure 8.2A.
Bit 5 / Receive All Zeros (RA0). A latched read only alarm status bit which is set when 31 consecutive
zeros are received. Allowed to be cleared once a one is received.
相关PDF资料 |
PDF描述 |
|---|---|
| DS3131 | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3112+ | 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3112+W | 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3112D1 | 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3112D1+ | 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3112DK | 功能描述:网络开发工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
发布紧急采购，3分钟左右您将得到回复。