参数资料
| 型号： | DS33R11DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/44页 |
| 文件大小： | 0K |
| 描述： | KIT DESIGN FOR DS33R11 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 设计资源： | DS33R11DK Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网 |
| 已用 IC / 零件： | DS33R11 |
| 已供物品： | 板 |
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DS33R11DK/DS33ZH11DK
LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS
The DS33Z11DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a
description of these signals, given in order of appearance on the PC board, from top to bottom then left to right
(with the board held so that the RS232 connector is on the left edge).
Table 2. Main Board PC Board Configuration
SILKSCREEN
REFERENCE
GROUND
(banana plug)
VDD 3.3V
(banana plug)
J01
J02
SW01
FUNCTION
Power supply ground
Power supply VDD
JTAG
RS-232 DB9
connector
Reset
BASIC
SETTING
—
—
—
—
SCHEMATIC
PAGE
2
2
17
14
12
DESCRIPTION
System power. Always connected
to power supply. Connectors are
provided at the top left and bottom
right of board. Connect either set to
power supply.
JTAG interface for Lattice EC3
FPGA.
RS-232 DB9 connector, operates in
ASCII mode at 57.6K baud, 8, N, 1.
Drives reset controller U01.
Displays interrupt status of
DS01
LED
—
15
DS33R11 (lit when interrupt is
asserted).
Displays Queue overflow status of
DS02
LED
7
DS33R11 (lit when Queue
overflows).
J04
J03
J05
J06
Y01
J07, J08
OnCe BDM
Flash VPP
JTAG
JTAG
Clock
Addr / Dat
—
3.3V
—
—
—
—
14
14
10
11
11
16
Debug connector for processor.
Jumper for driving MMC2107 flash
VPP to 5V .
JTAG interface for DS2155 portion
of DS33R11.
JTAG interface for DS33Z11
portion of DS33R11.
Oscillator for DS2155 portion of the
DS33R11.
Address and Databus Test points
for DS33R11.
J09
J09.2+J09.4
J09.4+J09.6
Configuration pins
(See next two rows
for details.)
Removed
Driver Enable
Schematic
Page16
Not installed
Installed
Configuration switches for selecting device driver
behavior. Additional detail given below.
Pin J09.2 has been removed. Jumpering this pin to
J09.4 causes a conflict with J09.6 FPGA pin.
Enables device driver and interrupt handler when
jumper is installed.
Causes device to select serial link TCLK = RCLK
J09.8+J09.10
RCLK select (FPGA)
User selection
when jumpered. When not jumpered TCLK =
MCLK.
Y02
Ethernet PHY Clock
—
3
25.000MHz clock for DS33R11
Ethernet PHY.
Must be set with pins 1+2
JP03
Clock select
Pins 1+2
Jumpered
3
jumpered. SDRAM oscillator does
not meet jitter requirement of the
Ethernet PHY.
J10
J11
Jumper
Jumper
Installed
Installed
10
10
Connects DS33R11 receive serial
lines.
Connects DS33R11 transmit serial
lines.
12 of 44
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