参数资料
型号: DS33R11DK
厂商: Maxim Integrated Products
文件页数: 8/44页
文件大小: 0K
描述: KIT DESIGN FOR DS33R11
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
设计资源: DS33R11DK Gerber Files
标准包装: 1
主要目的: 接口,以太网
已用 IC / 零件: DS33R11
已供物品:

DS33R11DK/DS33ZH11DK
SYSTEM FLOORPLAN
10/100 ETHERNET PHY AND
DS33R11/DS33ZH11 DESIGN KIT
MAGNETICS
DS3150
T3E3 LIU
TRANSFORMER AND NETWORK
CONNECTIONS (T3E3)
LEDs
TEST POINTS
BACKPLANE JUMPERS—TO DS33ZH11
LEDs
DS33R11
SDRAM
DS3150
T3E3 LIU
TRANSFORMER AND NETWORK
CONNECTIONS (T1E1)
MICROPROCESSOR
AND SERIAL PORT
(57600-8-N-1)
TEST POINTS
EEPROM
LEDs
TRANSFORMER AND NETWORK
CONNECTIONS (T1E1)
(CONFIG)
DS33ZH11
SDRAM
10/100 ETHERNET PHY AND
MAGNETICS
PC BOARD ERRATA
?
?
?
?
?
Center tap of T02 was not pulled to V3_3 in DS33R11DK/DS33ZH11DK01A0 revision (page 23 in schematic).
Pin T02.2 is pulled to V3_3 with a wire in the DS33R11DK/DS33ZH11DK01A0 revision.
Reference designators were assigned for R1, R2 and R01, R02. R1 and R2 will be renamed in the next design.
Component R1, R2 and Y05 are on bottom of the PC board but do not have the same prefix as other
components on the bottom side.
Silkscreen for J36.6 is mislabeled. It reads “RT0” but should read “RT1.”
Oscillators Y03 and YB03 are not suitable for use as input clocks for the Ethernet PHY. Because of this, the
oscillators will only be used as the SDRAM oscillators. These oscillators generate too much jitter to function as
the input clock for the PHY. This requires that the PHY is driven by the default oscillator, YB04 and YB02.
Jumpers JP03 and JP11 have been modified to prevent accidental selection of the wrong oscillator.
8 of 44
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