参数资料
| 型号： | DS33R11DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/44页 |
| 文件大小： | 0K |
| 描述： | KIT DESIGN FOR DS33R11 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 设计资源： | DS33R11DK Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网 |
| 已用 IC / 零件： | DS33R11 |
| 已供物品： | 板 |
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DS33R11DK/DS33ZH11DK
SILKSCREEN
REFERENCE
FUNCTION
BASIC
SETTING
SCHEMATIC
PAGE
DESCRIPTION
J31
J31.1
J31.3
J31.5
J31.7
Configuration pins
(See next 10 rows for
details)
DS21348 pin (MM1)
DS21348 pin (MM0)
DS21348 pin
(LOOP1)
DS21348 pin
(LOOP0)
Pin bias for DS21348. When not jumpered, this pin
is pulled to ground, jumper drives pin to VCC. A
basic description of the pin function is given below.
Refer to the data sheet for full details.
Monitor mode selection. See Table 2-11 in the
DS21348 data sheet.
Loop 1, Loop 0:
11 = RLB
10 = LLB
01 = ALB
J31.9
J31.11
J31.13
DS21348 pin (TX1)
DS21348 pin (TX0)
DS21348 pin (TPD)
Schematic
Page 25
Transmit data control (pattern vs. TPOS/TNEG)
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the
TTIP and TRING pins
0 = update RNEG/RPOS on rising edge of RCLK;
J31.15
J31.17
J31.19
J36
J36.2
J36.4
DS21348 pin (CES)
DS21348 pin
(TEST)
DS21348 pin
(PBTS/RT0)
Configuration pins
(See next three rows
for details.)
DS21348 pin (L1)
DS21348 pin (L2)
sample TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK;
sample TPOS/TNEG on rising edge of TCLK
Set high to tri-state all outputs and I/O pins.
Selects receive termination in conjunction with RT1.
Pin bias for DS21348. When not jumpered, this pin
is pulled to ground, jumper drives pin to VCC. A
basic description of the pin function is given below.
Refer to the data sheet for full details.
Transmit LIU waveshape select bits. (Refer to the
DS21348 data sheet Table 7-1 and 7-2.)
Transmit LIU waveshape select bits. (Refer to the
DS21348 data sheet Table 7-1 and 7-2.)
The silkscreen on this pin is mislabeled. Should
J36.6
JP10
DS15
J40, J41
DS21348 pin (RT1)
Clock selection
LED
Network connection
Schematic
Page 25
read RT1 with a function of selecting receive
termination.
25 —
25 —
24 —
J27
J26
JPB01
J30, J33
DS33ZH11 pin
(MODEC1)
DS33ZH11 pin
(HWMODE)
Jumper
Test points
21
21
21
26
—
—
—
Test points for MII interface
between PHY and DS33ZH11.
Must be set with pins 1+2
JP11
Clock selection
Pins 2+3
jumpered
18
jumpered. SDRAM oscillator does
not meet jitter requirement of the
Ethernet PHY.
Installation forces Ethernet PHY
J32, J35, J34
Jumpers
Not installed
26
mode. When not installed, the PHY
autonegotiates its settings
15 of 44
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