参数资料
型号: DS33R11DK
厂商: Maxim Integrated Products
文件页数: 16/44页
文件大小: 0K
描述: KIT DESIGN FOR DS33R11
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
设计资源: DS33R11DK Gerber Files
标准包装: 1
主要目的: 接口,以太网
已用 IC / 零件: DS33R11
已供物品:

DS33R11DK/DS33ZH11DK
SILKSCREEN
REFERENCE
FUNCTION
BASIC
SETTING
SCHEMATIC
PAGE
DESCRIPTION
Activity LEDs for Ethernet PHY. Tx
DS19, DS20,
DS21
LED
19
lights when PHY sends a packet;
Link lights when the PHY has found
a link partner.
DS16, DS17,
DS18
SW02
GROUND
(banana plug)
VDD 3.3V
(banana plug)
YB01
YB02
LED
Reset button
Power supply ground
Power supply VDD
DS3150 MCLK
DS21348 MCLK
19
19
2
2
23
25
Ethernet PHY mode LEDs. Used
for display of Speed, Duplex, and
Collision.
Redundant power supply
connection (see top left of board).
Redundant power supply
connection (see top left of board).
44.736MHz, for use with DS3150 in
T3 mode (bottom side of PC board)
1.544MHz, for use with DS21348 in
T1 mode (bottom side of PC board)
25.000MHz driver for DS33ZH11
YB04
Ethernet clock
18
Ethernet PHY (bottom side of PC
board).
100MHz SDRAM clock for
YB03
SDRAM clock
21
DS33ZH11 (bottom side of PC
board).
2.048MHz, for use with DS21348 in
YB05
Spare oscillator
25
E1 mode (bottom side of PC
board).
34.368MHz for use with DS3150 in
Y05
Spare oscillator
23
E3 mode (bottom side of PC
board).
ADDRESS MAP (ALL CARDS)
The external device address space begins at 0x81000000. All offsets given below are relative to this offset.
Table 3. Overview of Daughter Card Address Map
OFFSET
0X0000 to
0X0087
0X1000 to
0X1FFF
0X4000 to
0X4FFF
DEVICE
FPGA
DS33R11
DESCRIPTION
Processor board identification
DS33R11 Ethernet to Serial Engine. Uses
CS_X1.
T1E1 portion of DS33R11. Uses CS_X4.
Registers in the DS33R11 can be easily modified using the ChipView host-based user-interface software with the
definition files previously mentioned.
DS33R11 INFORMATION
For more information about the DS33R11, refer to the DS33R11 data sheet available on our website at
16 of 44
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