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参数资料
| 型号： | DS3882E+T&R/C |
| 厂商： | Maxim Integrated |
| 文件页数： | 12/31页 |
| 文件大小： | 0K |
| 描述： | IC AUTO CCFL CTRLR 2CH 28-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | CCFL 控制器 |
| 频率： | 40 ~ 100 kHz |
| 电流 - 电源： | 12mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
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Dual-Channel Automotive CCFL Controller
non-zero PWM code to the BPWM register disables the
BRIGHT pin and enables I 2 C burst dimming control.
Setting the 7-bit PWM code to 0000001b causes the
DS3882 to operate with the minimum burst duty cycle,
while a setting of 1111111b causes a 100% burst duty
cycle. For settings between these two codes, the duty
cycle varies linearly between the minimum and 100%.
Analog Dimming
Analog dimming changes the brightness by increasing
or decreasing the lamp current. The DS3882 accom-
plishes this by making small shifts to the lamp regula-
tion voltage, V LRT (see Figure 2). Analog dimming is
only possible by software communication with the lower
five bits (LC4–LC0) in the BLC register. This function is
not pin controllable. The default power-on state of the
LC bits is 00000b, which corresponds to 100% of the
nominal current level. Therefore on power-up, analog
dimming does not interfere with burst dimming func-
tionality if it is not desired. Setting the LC bits to 11111b
reduces the lamp current to 35% of its nominal level. For
LC values between 11111b and 00000b, the lamp cur-
rent varies linearly between 35% and 100% of nominal.
an external resistor at the LOSC. In this case, the
DS3882 can act as a lamp frequency source because
the lamp clock is output at the LSYNC I/O pin for
synchronizing any other DS3882s configured as lamp
frequency receivers. While DS3882 is sourcing lamp
frequency to other DS3882 ’s and spread-spectrum
modulation or frequency step features are enabled, the
LSYNC output is not affected by either EMI suppression
features. The DS3882 acts as a lamp frequency receiv-
er when the lamp clock is supplied externally. In this
case, a 40kHz to 100kHz clock must be supplied at the
LSYNC I/O. The external clock can originate from the
LSYNC I/O of a DS3882 configured as a lamp frequency
source or from some other source.
DPWM RECEIVER
BRIGHT
Lamp Frequency Configuration
The DS3882 can generate its own lamp frequency
clock internally (set LFSS = 0 in CR1), which can then
be sourced to other DS3882s if required, or the lamp
clock can be supplied from an external source (set
LFSS = 1 in CR1). When the lamp clock is internally
DPWM
SIGNAL
22.5Hz TO 440Hz
PSYNC
POSC
generated, the frequency (40kHz to 100kHz) is set by
RESISTOR-SET DIMMING CLOCK
Figure 4. DPWM Receiver Configuration
EXTERNAL DIMMING CLOCK
ANALOG DIMMING
2.0V
ANALOG DIMMING
2.0V
CONTROL VOLTAGE
DPWM
SIGNAL
0.5V
BRIGHT
PSYNC
CONTROL VOLTAGE
DPWM
SIGNAL
0.5V
BRIGHT
PSYNC
22.5Hz TO 440Hz
POSC
EXTERNAL
22.5Hz TO 440Hz
POSC
EXTERNAL RESISTOR
SETS DPWM RATE
Figure 3. DPWM Source Configuration Options
DPWM CLOCK
22.5Hz to 440Hz
12
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