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参数资料
| 型号： | DS3882E+T&R/C |
| 厂商： | Maxim Integrated |
| 文件页数： | 19/31页 |
| 文件大小： | 0K |
| 描述： | IC AUTO CCFL CTRLR 2CH 28-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | CCFL 控制器 |
| 频率： | 40 ~ 100 kHz |
| 电流 - 电源： | 12mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
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Dual-Channel Automotive CCFL Controller
Table 2. Status Register 1 (SR1) [SRAM, E0h]
BIT
R/W
POWER-UP
DEFAULT
NAME
FUNCTION
Fault Condition—Real Time. A real-time bit that indicates the current operating status of
0
R
0
FAULT_RT
channel 1.
0 = Normal condition
1 = Fault condition
1
2
3
4
5
6
7
R
R
R
R
R
R
R
0
0
0
0
0
0
0
FAULT_L
STO_L
OV_L
LOUT_L
LOC_L
SVML_RT
SVMH_RT
Fault Condition—Latched. A latched bit that is set when the channel enters a fault
condition. This bit is cleared when read, regardless of the current state of fault.
Lamp Strike Timeout—Latched. A latched bit that is set when the lamp fails to strike.
This bit is cleared when read.
Overvoltage—Latched. A latched bit that is set when a lamp overvoltage is present for
at least 64 lamp cycles. This bit is cleared when read.
Lamp Out—Latched. A latched bit that is set when a lamp out is detected. This bit is
cleared when read.
Lamp Overcurrent—Latched. A latched bit that is set when a lamp overcurrent is
detected. This bit is cleared when read.
Supply Voltage Monitor Low—Real Time. A real-time bit that reports the comparator
output of the SVML pin.
Supply Voltage Monitor High—Real Time. A real-time bit that reports the comparator
output of the SVMH pin.
Note 1: Writing to this register has no effect on it.
Note 2: See Figure 8 for more details on how the status bits are set.
Note 3: SR1 is cleared when any of the following occurs:
? V CC drops below the UVLO threshold
? the SVML or SVMH thresholds are crossed
? the PDN hardware pin goes high
? the PDNE software bit is written to a logic 1
? the channel is disabled by the CH1D control bit
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