参数资料
| 型号： | DS3994Z+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC CCFL CNTRLR 4CH 28-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | CCFL 控制器 |
| 频率： | 20 ~ 80 kHz |
| 电流 - 电源： | 9mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
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4-Channel Cold-Cathode
Fluorescent Lamp Controller
Channel Phasing
The lamp-frequency MOSFET gate turn-on times are
equally phased among the four channels during the
burst period. This reduces the inrush current that would
result from all lamps switching simultaneously, and
hence eases the design requirements for the DC supply.
Figure 2 details how the four channels are phased. Note
that it is the lamp frequency signals that are phased,
NOT the DPWM signals. See the Burst Dimming Stagger
(BDS) Functionality section for details or to adjust the
DPWM signals of each channel.
Lamp Dimming Control (DPWM)
The DS3994 uses a digital pulse-width modulated
(DPWM) signal (22.5Hz to 440Hz) to provide efficient
and precise lamp dimming. During the high period of
the DPWM cycle, the lamps are driven at the selected
lamp frequency (20kHz to 80kHz) as shown in Figure 7.
This part of the cycle is called the “burst ” period
because of the lamp frequency burst that occurs dur-
ing this time. During the low period of the DPWM cycle,
the controller disables the MOSFET gate drivers so the
lamps are not driven. This causes the current to stop
flowing in the lamps, but the time is short enough to keep
the lamps from de-ionizing. Dimming is increased/
decreased by adjusting (i.e., modulating) the duty cycle
of the DPWM signal.
The DS3994 can generate its own DPWM signal internally
(set DPSS = 0 in CR1), which can then be sourced to
other DS3994s if required, or the DPWM signal can be
supplied from an external source (set DPSS = 1 in CR1).
4
1
2
3
4
1
2
3
4
1
2
3
4
CHANNEL
SEQUENCE
VARIABLE
GA1
GB1
GA2
GB2
GA3
GB3
GA4
GB4
MOSFET GATE-
DRIVE SIGNALS AT
LAMP FREQUENCY
Figure 2. Channel Phasing Detail
MOSFET
GATE DUTY
CYCLE
DIMMING CLOCK (DPWM)
FREQUENCY
10
____________________________________________________________________
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