参数资料
| 型号： | DS3994Z+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 11/28页 |
| 文件大小： | 0K |
| 描述： | IC CCFL CNTRLR 4CH 28-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | CCFL 控制器 |
| 频率： | 20 ~ 80 kHz |
| 电流 - 电源： | 9mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
4-Channel Cold-Cathode
Fluorescent Lamp Controller
RESISTOR-SET DIMMING CLOCK
2.0V
OR
2.0V
OR
EXTERNAL DIMMING CLOCK
ANALOG DIMMING
CONTROL VOLTAGE
0.5V
OR
0.0V
3.3V
BRIGHT
ANALOG DIMMING
CONTROL VOLTAGE
0.5V
OR
0.0V
3.3V
BRIGHT
DPWM
SIGNAL
22.5Hz TO 440Hz
PSYNC (OUTPUT)
POSC
DPWM
SIGNAL
EXTERNAL
22.5Hz TO 440Hz
PSYNC (OUTPUT)
POSC
RESISTOR TO SET THE
DIMMING FREQUENCY
DIMMING CLOCK
22.5Hz TO 440Hz
Figure 3. DPWM Source Configuration Options
Table 1. BRIGHT Analog Dimming Input Slope and Voltage Range Configuration
CR2.7
0
0
1
1
CR3.0
0
1
0
1
RANGE
0.5 to 2V
0.5 to 2V
0 to 3.3V
0 to 3.3V
SLOPE
Positive
Negative
Positive
Negative
MINIMUM BRIGHTNESS
0.5V
2.0V
0V
3.3V
MAXIMUM BRIGHTNESS
2.0V
0.5V
3.3V
0V
Lamp Dimming Control (DPWM)
When the DPWM signal is generated internally, its duty
cycle (and, thus, the lamp brightness) is controlled by a
BRIGHT
user-applied analog voltage at the BRIGHT input. Users
can select a positive or negative slope for the bright
DPWM
SIGNAL
22.5Hz TO 440Hz
PSYNC (INPUT)
POSC
pin’s dimming input as well as the voltage range. If
SLOPE = 0 in CR3, then the slope is positive. This
means that a BRIGHT voltage less than the minimum
voltage causes the DS3994 to operate with the minimum
burst duty cycle, providing the lowest brightness set-
ting, while any voltage greater than the maximum volt-
Figure 4. DPWM Receiver Configuration
To generate the DPWM signal internally, the DS3994
requires a clock (referred to as the dimming clock) to
set the DPWM frequency. The user can supply the dim-
ming clock by setting POSCS = 1 in CR1 and applying
an external 22.5Hz to 440Hz signal at the POSC pin, or
DS3994’s clock can be generated by the DS3994’s
oscillator (set POSCS = 0 in CR1), in which case the
frequency is set by an external resistor at the POSC
pin. These two dimming clock options are shown in
Figure 3. Regardless of whether the dimming clock is
generated internally or sourced externally, the POSCR0
and POSCR1 bits in CR2 must be set to match the
desired dimming clock frequency.
age causes a 100% burst duty cycle (i.e., lamps always
being driven), which provides the maximum brightness.
For voltages between the minimum voltage and the
maximum voltage, the duty cycle varies linearly between
the minimum and 100%.
The internally generated DPWM signal is available at
the PSYNC I/O pin (set RGSO = 0 in CR1) for sourcing
to other DS3994s, if any, in the circuit. This allows all
DS3994s in the system to be synchronized to the same
DPWM signal. The DS3994 that is generating the
DPWM signal for other DS3994s in the system is
referred to as the DPWM source.
______________________________________________________________________________________________________
11
相关PDF资料 |
PDF描述 |
|---|---|
| DS4303R-U+ | IC VREF SERIES ADJ SOT-23-5 |
| DS4510U-5/T&R | IC SUPERVISOR W/NV MEM 5-USOP |
| DS4510U+ | IC SUPERVISOR W/NV MEM 10-USOP |
| DW-16-12-G-D-665 | CONN HEADER 32POS DUAL 2.54MM AU |
| DW-22-12-G-T-670 | CONN HEADER 66POS TRIPLE 2.54MM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3CC | 制造商:Thomas & Betts 功能描述:30A,MG,CUP CAP |
| DS3DS3801 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3-LD-015 | 制造商:IDEC CORPORATION 功能描述:957600120 Sensor light grids |
| DS3-LD-030 | 制造商:IDEC CORPORATION 功能描述:957600140 Light grids |
| DS3-LD-045 | 制造商:IDEC CORPORATION 功能描述:957600160 Light grids |
发布紧急采购，3分钟左右您将得到回复。