参数资料
| 型号： | DS3994Z+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 21/28页 |
| 文件大小： | 0K |
| 描述： | IC CCFL CNTRLR 4CH 28-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | CCFL 控制器 |
| 频率： | 20 ~ 80 kHz |
| 电流 - 电源： | 9mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
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4-Channel Cold-Cathode
Fluorescent Lamp Controller
F5h: Control Register 2 (CR2)
BIT
0
1
NAME
UMWP
POSCR0
FUNCTION
User Memory Write Protect
0 = User Memory Write Access Blocked
1 = User Memory Write Access Permitted
DPWM Oscillator Range Select. When using an external source for the dimming clock, these bits must
be set to match the external oscillator’s frequency. When using a resistor to set the dimming
frequency, these bits plus the external resistor control the frequency.
POSCR1
POSCR0
DIMMING CLOCK (DPWM)
FREQUENCY RANGE (Hz)
K
(k Ω -kHz)
2
POSCR1
0
0
1
1
0
1
0
1
22.5 to 55.0
45 to 110
90 to 220
180 to 440
1
2
4
8
3
4
Reserved
Reserved
Reserved. Should be set to one.
Reserved. Should be set to zero.
Lamp Disable. Used to disable channels if all 4 are not required for an application.
5
6
LD0
LD1
LD1
0
0
1
1
LD0
0
1
0
1
CHANNELS DISABLED
All Channels Enabled
4
2/4
1/2/4
NUMBER OF ACTIVE
LAMP CHANNELS
4
3
2
1
Bright Voltage Range Select.
7
BVRS
0 = 0.5V to 2.0V
1 = 0.0V to 3.3V
F8–FBh: Burst Dimming Stagger (BDS1/2/3/4)
BIT
0
1
2
3
4
5
6
7
NAME
BDSC0
BDSC1
BDSC2
BDSC3
BDSC4
BDSC5
BDSC6
BDSC7
FUNCTION
8-Bit Programmable Counter That Staggers the Start of Burst Dimming. 00h = 0ms stagger. Setting
the stagger longer than the burst dimming cycle results in the channel never turning on. See Table 2.
____________________________________________________________________
21
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