参数资料
| 型号： | DS3994Z+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 12/28页 |
| 文件大小： | 0K |
| 描述： | IC CCFL CNTRLR 4CH 28-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 类型： | CCFL 控制器 |
| 频率： | 20 ~ 80 kHz |
| 电流 - 电源： | 9mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
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4-Channel Cold-Cathode
Fluorescent Lamp Controller
When the DPWM signal is provided by an external
source, either from the PSYNC pin of another DS3994 or
from some other user-generated source, it is input into the
PSYNC I/O pin of the DS3994. In this mode, the BRIGHT
and POSC inputs are disabled and should be grounded
(see Figure 4). When multiple DS3994s are used in a
design, DS3994s configured to use externally generated
DPWM signals are referred to as DPWM receivers.
Burst Dimming Stagger (BDS) Functionality
The DS3994 also features burst dimming stagger (BDS)
functionality integrated into the burst dimming con-
troller. BDS is useful to reduce the current ripple on the
DC supply as well as improve the visual motion
response of the LCD panel. This feature allows users to
enter a digital code into each channel independent
register (BDS1/2/3/4) that would delay the start of each
burst period. The 8-bit BDS code can be calculated by
using Table 2 and the following equations.
Table 2. Multiplication Factor M, Based on Lamp Frequency Oscillator and DPWM
Frequency Oscillator
M, LAMP CYCLE PERIOD MULTIPLICATION FACTOR
POSCR1
(CR2.2)
0
0
1
1
POSCR0
(CR2.1)
0
1
0
1
SELECTED PWM
OSCILLATOR RANGE (Hz)
22.5 to 55
45 to 110
90 to 220
180 to 440
LAMP OSCILLATOR = 40
TO 80kHz (LOFS = 0)
8
4
2
1
LAMP OSCILLATOR = 20
TO 40kHz (LOFS = 1)
8
4
2
1
BDS_Resolution =
M
f LF : OSC
BDS_Delay = BDS_Resolution x BDS_8-Bit_Value
If a BDS_Delay is used that is longer than the burst peri-
od, then the gate drivers, GA and GB, have no output.
For example, assume a lamp frequency of 50kHz and a
burst frequency of 167Hz. The step resolution of the
CHANNEL 1
BURST DIMMING CYCLE (167Hz/6ms)
burst-dimming stagger would be 40μs (2/50,000). To
achieve equal stagger, as shown in Figure 5, the
BDS1/2/3/4 registers would be programmed as
described in Table 3.
CHANNEL 2
CHANNEL 3
CHANNEL 4
1.5ms
3.0ms
4.5ms
Figure 5. Example Burst Dimming Stagger Cycle
Table 3. Example BDS1/2/3/4 Programmed Values
CHANNEL
1
2
3
4
REGISTER
BDS1
BDS2
BDS3
BDS4
DESIRED STAGGER (ms)
0
1.5
3.0
4.5
STEP RESOLUTION (μs)
40
40
40
40
COUNT
0
38
75
113
PROGRAMMED VALUE
00h
26h
4Bh
71h
12
____________________________________________________________________
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