- 您现在的位置：买卖IC网 > PDF目录19503 > DSP56303AG100 (Freescale Semiconductor)IC DSP 24BIT 100MHZ 144-LQFP PDF资料下载
参数资料
| 型号： | DSP56303AG100 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 76/108页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 100MHZ 144-LQFP |
| 特色产品： | DSP56303 24-bit Digital Signal Processor |
| 标准包装： | 60 |
| 系列： | DSP563xx |
| 类型： | 定点 |
| 接口： | 主机接口，SSI，SCI |
| 时钟速率： | 100MHz |
| 非易失内存： | ROM（576 B） |
| 芯片上RAM： | 24kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页当前第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页
Power
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
1-3
1.1 Power
1.2 Ground
Table 1-2.
Power Inputs
Power Name
Description
VCCP
PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with
an extremely low impedance path to the VCC power rail.
VCCQ
Quiet Power—An isolated power for the core processing logic. This input must be isolated externally from all other chip
power inputs.
VCCA
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally
to all other chip power inputs,
except VCCQ.
VCCD
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all
other chip power inputs,
except VCCQ.
VCCC
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other
chip power inputs,
except VCCQ.
VCCH
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power
inputs,
except VCCQ.
VCCS
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied
externally to all other chip power inputs,
except VCCQ.
Note: The user must provide adequate external decoupling capacitors for all power connections.
Table 1-3.
Grounds1
Ground Name
Description
GNDP
PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip
package.
GNDP1
PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground.
GNDQ
2
Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied externally to all other
chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling capacitors.
GNDA
2
Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This connection must be tied
externally to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external
decoupling capacitors.
GNDD
2
Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection must be tied externally
to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling
capacitors.
GNDC
2
Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be tied externally to all
other chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling
capacitors.
GNDH
2
Host Ground—An isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other chip
ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling capacitors.
GNDS
2
ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be
tied externally to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external
decoupling capacitors.
GND3
Ground—Connected to an internal device ground plane.
Notes:
1.
The user must provide adequate external decoupling capacitors for all GND connections.
2.
These connections are only used on the TQFP package.
3.
These connections are common grounds used on the MAP-BGA package.
相关PDF资料 |
PDF描述 |
|---|---|
| V300A3V3E264BL3 | CONVERTER MOD DC/DC 3.3V 264W |
| KRM55WR72A156MH01K | CAP CER 15UF 100V 20% X7R 2220 |
| VI-B51-CY-F2 | CONVERTER MOD DC/DC 12V 50W |
| MLP2012S4R7M | INDUCTOR MULTILAYER 4.7UH 0805 |
| DSPB56374AE | IC DSP 24BIT 150MHZ 52-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56303AG100B1 | 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56303AG100R2 | 功能描述:数字信号处理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56303EVM | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP56303 Eval Kit RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56303EVMCL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56303EVM DSP56303EVM Kit Contents List |
| DSP56303EVMUM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56303 EVM Users Manual |
发布紧急采购，3分钟左右您将得到回复。