参数资料
型号: DSP56852VFE
厂商: Freescale Semiconductor
文件页数: 45/48页
文件大小: 0K
描述: IC DSP 16BIT 120MHZ 81-MAPBGA
标准包装: 348
系列: 568xx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 120MHz
连通性: EBI/EMI,SCI,SPI,SSI
外围设备: POR,WDT
输入/输出数: 11
程序存储器容量: 12KB(6K x 16)
程序存储器类型: SRAM
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.3 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 81-LFBGA
包装: 托盘
56852 Technical Data, Rev. 8
6
Freescale Semiconductor
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description of and proper design with
the 56852. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
Table 1-1 DSP56852 Chip Documentation
Topic
Description
Order Number
DSP56800E
Reference Manual
Detailed description of the 56800E architecture, 16-bit
controller core processor and the instruction set
DSP56800ERM
DSP56852
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56852
DSP56852UM
DSP56852
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
DSP56852
Errata
Details any chip issues that might be present
DSP56852E
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
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