- 您现在的位置：买卖IC网 > PDF目录1917 > DSP56852VFE (Freescale Semiconductor)IC DSP 16BIT 120MHZ 81-MAPBGA PDF资料下载
参数资料
| 型号： | DSP56852VFE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 120MHZ 81-MAPBGA |
| 标准包装： | 348 |
| 系列： | 568xx |
| 核心处理器： | 56800E |
| 芯体尺寸： | 16-位 |
| 速度： | 120MHz |
| 连通性： | EBI/EMI，SCI，SPI，SSI |
| 外围设备： | POR，WDT |
| 输入/输出数： | 11 |
| 程序存储器容量： | 12KB（6K x 16） |
| 程序存储器类型： | SRAM |
| RAM 容量： | 4K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 3.3 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 81-LFBGA |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
56852 Technical Data, Rev. 8
14
Freescale Semiconductor
D5
RESET
Input
Reset (RESET)—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial Chip Operating mode is
latched from the D[15:13] pins. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed number of
internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary not
to reset the JTAG/Enhanced OnCE module. In this case, assert
RESET, but do not assert TRST.
C6
TCK
Input
Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/Enhanced
OnCE port. The pin is connected internally to a pull-down resistor.
B7
TDI
Input
Test Data Input (TDI)—This input pin provides a serial input data
stream to the JTAG/Enhanced OnCE port. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
A8
TDO
Output
Test Data Output (TDO)—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in
the Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
C7
TMS
Input
Test Mode Select Input (TMS)—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
D6
TRST
Input
Test Reset (TRST)—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment, since the Enhanced
OnCE/JTAG module is under the control of the debugger. In this case it
is not necessary to assert TRST when asserting RESET. Outside of a
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the Enhanced OnCE/JTAG module
on the device.
Note:
For normal operation, connect TRST directly to VSS. If the design is
to be used in a debugging environment, TRST may be tied to VSS through a 1K
resistor.
B8
DE
Input/Output
Debug Even (DE)— is an open-drain, bidirectional, active low signal.
As an input, it is a means of entering Debug mode of operation from an
external command controller. As an output, it is a means of
acknowledging that the chip has entered Debug mode.
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No.
Signal Name
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| DSP56854FGE | IC DSP 16BIT 120MHZ 128-LQFP |
| DSP56855BUE | IC DSP 16BIT 120MHZ 100-LQFP |
| DSP56857BUE | IC DSP 16BIT 120MHZ 100-LQFP |
| DSP56858FVE | IC DSP 16BIT 120MHZ 144-LQFP |
| DSP56F801FA80E | IC DSP 60MHZ 16KB FLASH 48-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56853 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56853E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56853FG120 | 功能描述:数字信号处理器和控制器 - DSP, DSC 120Mhz/120MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56853FGE | 功能描述:数字信号处理器和控制器 - DSP, DSC 120Mhz/120MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56853PB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56853 Digital Signal Processor Product Brief |
发布紧急采购，3分钟左右您将得到回复。