参数资料
型号: DSP56852VFE
厂商: Freescale Semiconductor
文件页数: 48/48页
文件大小: 0K
描述: IC DSP 16BIT 120MHZ 81-MAPBGA
标准包装: 348
系列: 568xx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 120MHz
连通性: EBI/EMI,SCI,SPI,SSI
外围设备: POR,WDT
输入/输出数: 11
程序存储器容量: 12KB(6K x 16)
程序存储器类型: SRAM
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.3 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 81-LFBGA
包装: 托盘
Introduction
56852 Technical Data, Rev. 8
Freescale Semiconductor
9
Part 3 Signals and Package Information
All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are
enabled by default. Exceptions:
1. When a pin has GPIO functionality, the pull-up may be disabled under software control.
2. Mode pins D13, D14 and D15 have no pull-up.
3. TCK has a weak pull-down circuit always active.
4. Bidirectional I/O pullups automatically disable when the output is enabled.
This table is presented consistently with the Signals Identified by Functional Group figure.
1. BOLD entries in the Type column represents the state of the pin just out of reset.
2. Ouput(Z) means an output in a High-Z condition.
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA
Pin No.
Signal Name
Type
Description
E1
VDD
Logic Power —These pins provide power to the internal structures of
the chip, and should all be attached to VDD.
J5
VDD
E9
VDD
D1
VSS
Logic Power - GND—These pins provide grounding for the internal
structures of the chip and should all be attached to VSS.
J4
VSS
F9
VSS
C1
VDDIO
I/O Power —These pins provide power for all I/O and ESD structures of
the chip, and should all be attached to VDDIO.
H1
VDDIO
J7
VDDIO
G9
VDDIO
B9
VDDIO
A4
VDDIO
B1
VSSIO
I/O Power - GND—These pins provide grounding for all I/O and ESD
structures of the chip and should all be attached to VSS.
G1
VSSIO
J6
VSSIO
J9
VSSIO
C9
VSSIO
A5
VSSIO
B5
VDDA
Analog Power—These pins supply an analog power source
B6
VSSA
Analog Ground—This pin supplies an analog ground.
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