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型号： DSPIC33FJ12MC202T-I/SS
厂商： Microchip Technology
文件页数： 54/155页
文件大小： 0K
描述： IC DSPIC MCU/DSP 12K 28SSOP
产品培训模块： Asynchronous Stimulus
标准包装： 2,100
系列： dsPIC™ 33F
核心处理器： dsPIC
芯体尺寸： 16-位
速度： 40 MIP
连通性： I²C，IrDA，SPI，UART/USART
外围设备： 高级欠压探测/复位，电机控制 PWM，QEI，POR，PWM，WDT
输入/输出数： 21
程序存储器容量： 12KB（12K x 8）
程序存储器类型： 闪存
RAM 容量： 1K x 8
电压 - 电源 (Vcc/Vdd)： 3 V ~ 3.6 V
数据转换器： A/D 6x10b/12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 28-SSOP（0.209"，5.30mm 宽）
包装： 带卷 (TR)
2010 Microchip Technology Inc.
DS41303G-page 281
PIC18F2XK20/4XK20
20.2
Comparator Control
Each comparator has a separate control and Configu-
ration register: CM1CON0 for Comparator C1 and
CM2CON0 for Comparator C2. In addition, Compara-
tor C2 has a second control register, CM2CON1, for
controlling the interaction with Timer1 and simultane-
ous reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Regis-
ters 20-1 and 20-2, respectively) contain the control
and Status bits for the following:
Enable
Input selection
Reference selection
Output selection
Output polarity
Speed selection
20.2.1
COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
20.2.2
COMPARATOR INPUT SELECTION
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
20.2.3
COMPARATOR REFERENCE
SELECTION
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting
input
of
the
comparator.
See
Section 21.0
“VOLTAGE
REFERENCES”
for
more
information on the Internal Voltage Reference module.
20.2.4
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
CxOE bit of the CMxCON0 register must be set
Corresponding TRIS bit must be cleared
CxON bit of the CMxCON0 register must be set
20.2.5
COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 20-1 shows the output state versus input
conditions, including polarity control.
20.2.6
COMPARATOR SPEED SELECTION
The trade-off between speed or power can be opti-
mized during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propaga-
tion delay by clearing the CxSP bit to ‘0’.
20.3
Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 26.0
“Electrical Characteristics” for more details.
Note:
To use CxIN+ and C12INx- pins as analog
inputs, the appropriate bits must be set in
the ANSEL register and the corresponding
TRIS bits must also be set to disable the
output drivers.
Note 1: The CxOE bit overrides the PORT data
latch. Setting the CxON has no impact on
the port override.
2: The internal output of the comparator is
latched
with
each
instruction
cycle.
Unless
otherwise
specified,
external
outputs are not latched.
TABLE 20-1:
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
CxVIN- > CxVIN+
00
CxVIN- < CxVIN+
01
CxVIN- > CxVIN+
11
CxVIN- < CxVIN+
10
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