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参数资料
| 型号： | E28F320J5-120 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT |
| 中文描述： | 2M X 16 FLASH 5V PROM, 150 ns, PDSO56 |
| 封装： | 14 X 20 MM, TSOP-56 |
| 文件页数： | 17/51页 |
| 文件大小： | 651K |
| 代理商： | E28F320J5-120 |
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28F320J5 and 28F640J5
24
Datasheet
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.
4.3
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following
the command write, read cycles from addresses shown in Figure 5 retrieve the manufacturer,
device, block lock configuration and master lock configuration codes (see Table 13 for identifier
code values). To terminate the operation, write another valid command. Like the Read Array
command, the Read Identifier Codes command functions independently of the VPEN voltage and
RP# can be VIH or VHH. This command is valid only when the WSM is off or the device is
suspended. Following the Read Identifier Codes command, the following information can be read:
Table 13. Primary Vendor-Specific Extended Query
Offset(1)
P= 31h
Length
Description
(Optional Flash Features and Commands)
Add.
Hex
Code
Value
(P+0)h
3
Primary extended query table
31:
--50
“P”
(P+1)h
Unique ASCII string“PRI”
32:
--52
“R”
(P+2)h
33:
--49
“I”
(P+3)h
1
Major version number, ASCII
34:
--31
“1”
(P+4)h
1
Minor version number, ASCII
35:
--31
“1”
(P+5)h
4
Optional feature and command support (1=yes, 0=no)
36:
--0A
(P+6)h
bits 9–31 are reserved; undefined bits are “0.” If bit 31 is
37:
--00
(P+7)h
“1” then another 31 bit field of optional features follows at
38:
--00
(P+8)h
theend of thebit-30field.
39:
--00
bit 0 Chip erase supported
bit 0 = 0
No
bit 1 Suspend erase supported
bit 1 = 1
Yes
bit 2 Suspend program supported
bit 2 = 0
No
bit 3 Legacy lock/unlock supported
bit 3 = 1
Yes
bit 4 Queued erase supported
bit 4 = 0
No
(P+9)h
1
Supported functions after suspend: read Array, Status,
Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
3A:
--01
bit 0 Program supported after erase suspend
bit 0 = 1
Yes
(P+A)h
2
Block status register mask
3B:
--01
(P+B)h
bits 2–15 are Reserved; undefined bits are “0”
3C:
--00
bit 0 Block Lock-Bit Status register active
bit 0 = 1
Yes
bit 1 Block Lock-Down Bit Status active
bit 1 = 0
No
(P+C)h
1
VCC logic supply highest performance program/erase
voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
3D:
--50
5.0 V
(P+D)h
1
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
3E:
--00
0.0 V
(P+E)h
Reserved for Future Use
3F:
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| E28F320J5A-120 | 制造商:Intel 功能描述: |
| E28F320S5-110 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| E28F320S5-90 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| E28F400B5B60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| E28F400B5B80 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intel 功能描述: |
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