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参数资料
| 型号： | E28F320J5-120 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT |
| 中文描述： | 2M X 16 FLASH 5V PROM, 150 ns, PDSO56 |
| 封装： | 14 X 20 MM, TSOP-56 |
| 文件页数： | 9/51页 |
| 文件大小： | 651K |
| 代理商： | E28F320J5-120 |
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28F320J5 and 28F640J5
Datasheet
17
4.0
Command Definitions
When the VPEN voltage ≤ VPENLK, only read operations from the status register, query, identifier
codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program,
and lock-bit configuration operations.
Device operations are selected by writing specific commands into the CUI. Table 4 defines these
commands.
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
2. If the WSM is running, only DQ7 is valid; DQ15–DQ8 and DQ6–DQ0 float, whichplaces theminahigh-
impedance state.
Table 4.
Intel StrataFlash Memory Command Set Definitions(1,2)
Command
Scaleable
or Basic
Command
Set(2)
Bus
Cycles
Req’d.
Notes
First Bus Cycle
Second Bus Cycle
Oper(3)
Addr(4)
Data(5,6)
Oper(3)
Addr(4)
Data(5,6)
Read Array
SCS/BCS
1
Write
X
FFH
Read Identifier
Codes
SCS/BCS
≥ 2
7
Write
X
90H
Read
IA
ID
Read Query
SCS
≥ 2
Write
X
98H
Read
QA
QD
Read Status
Register
SCS/BCS
2
8
Write
X
70H
Read
X
SRD
Clear Status
Register
SCS/BCS
1
Write
X
50H
WritetoBuffer
SCS/BCS
> 2
9, 10,
11
Write
BA
E8H
Write
BA
N
Word/Byte
Program
SCS/BCS
2
12,13
Write
X
40H
or
10H
Write
PA
PD
Block Erase
SCS/BCS
2
11,12
Write
X
20H
Write
BA
D0H
Block Erase,
Program
Suspend
SCS/BCS
1
12,14
Write
X
B0H
Block Erase,
Program
Resume
SCS/BCS
1
12
Write
X
D0H
Configuration
SCS
2
Write
X
B8H
Write
X
CC
Set Read
Configuration
2
Write
X
60H
Write
RCD
03H
Set Block Lock-
Bit
SCS
2
Write
X
60H
Write
BA
01H
Clear Block
Lock-Bits
SCS
2
15
Write
X
60H
Write
X
D0H
Protection
Program
2Write
X
C0H
Write
PA
PD
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