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参数资料
| 型号： | EM6617SO24A |
| 元件分类： | MOSFETs |
| 英文描述： | 30V N-Channel PowerTrench MOSFET |
| 中文描述： | 30V的N沟道的PowerTrench MOSFET的 |
| 文件页数： | 35/67页 |
| 文件大小： | 824K |
| 代理商： | EM6617SO24A |
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EM6617
03/02 REV. C/442
Copyright
2002, EM Microelectronic-Marin SA
40
www.emmicroelectronic.com
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their mask
setting and not on the general interrupt enable status.
Whenever the EM6617 goes into HALT Mode the IntEn bit is automatically set to 1, thus allowing to resume
from halt mode with an interrupt. This behavior is blocked if SWBAuto is set high. In this case the peripheral
interrupts are disabled until the SWBAuto bit is reset low. Please refer also to the SWB chapter 9.
13.1 Interrupt control registers
Table 13.1.1 register RegIRQ1
Bit
Name
Reset
R/W
Description
3
IRQPA[3]
0
R/W*
Port A PA[3] interrupt request
2
IRQPA[2]
0
R/W*
Port A PA[2] interrupt request
1
IRQPA[1]
0
R/W*
Port A PA[1] interrupt request
0
IRQPA[0]
0
R/W*
Port A PA[0] interrupt request
W*; Writing of 1 clears the corresponding bit.
Table 13.1.2 register RegIRQ2
Bit
Name
Reset
R/W
Description
3
IRQHz1
0
R/W*
Prescaler interrupt request
2
IRQHz32/8
0
R/W*
Prescaler interrupt request
1
IRQEEP
0
R/W*
EEPROM interrupt request
0
IRQADC
0
R/W*
ADC interrupt request
W*; Writing of 1 clears the corresponding bit.
Table 13.1.3 register RegIRQ3
Bit
Name
Reset
R/W
Description
3--
2
IRQVLD
0
R/W*
VLD interrupt request
1
IRQCount0
0
R/W*
Counter interrupt request
0
IRQCntComp
0
R/W*
Counter interrupt request
W*; Writing of 1 clears the corresponding bit.
Table 13.1.4 register RegIRQMask1
Bit
Name
Reset
R/W
Description
3
MaskIRQPA[3]
0
R/W
Port A PA[3] interrupt mask
2
MaskIRQPA[2]
0
R/W
Port A PA[2] interrupt mask
1
MaskIRQPA[1]
0
R/W
Port A PA[1] interrupt mask
0
MaskIRQPA[0]
0
R/W
Port A PA[0] interrupt mask
Interrupt is not stored if the mask bit is 0.
Table 13.1.5 register RegIRQMask2
Bit
Name
Reset
R/W
Description
3
MaskIRQHz1
0
R/W
Prescaler interrupt mask
2
MaskIRQHz32/8
0
R/W
Prescaler interrupt mask
1
MaskIRQEEP
0
R/W
EEPROM interrupt mask
0
MaskIRQADC
0
R/W
ADC interrupt mask
Interrupt is not stored if the mask bit is 0.
Table 13.1.6 register RegIRQMask3
Bit
Name
Reset
R/W
Description
3--
2
MaskIRQVLD
0
R/W
VLD interrupt mask
1
MaskIRQCount0
0
R/W
Counter interrupt mask
0
MaskIRQCntComp
0
R/W
Counter interrupt mask
Interrupt is not stored if the mask bit is 0
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| EM6617TP28B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
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