参数资料
型号: EMC2103-1-KP-TR
厂商: STANDARD MICROSYSTEMS CORP
元件分类: 模拟信号调理
中文描述: SPECIALTY ANALOG CIRCUIT, QCC12
封装: 4 X 4 MM, ROHS COMPLIANT, QFN-12
文件页数: 49/89页
文件大小: 1243K
代理商: EMC2103-1-KP-TR
RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
SMSC EMC2103
53
Revision 0.90 (08-19-08)
DATASHEET
The Configuration 2 Register is software locked.
6.12
Interrupt Status Register
The Interrupt Status Register reports the operating condition of the EMC2103. If any of the bits are set
to a logic ‘1’ (other than HWS) then the ALERT pin will be asserted low if the corresponding channel
is enabled. Reading from the status register clears all status bits if the error conditions is removed. If
there are no set status bits, then the ALERT pin will be released.
The bits that cause the ALERT pin to be asserted can be masked based on the channel they are
associated with unless stated otherwise.
Bit 7 - EEPROM (EMC2103-4 only) - This bit is set to ‘1’ if the EEPROM loader circuitry detects an
error when writing data from the EEPROM. This bit is cleared when the register is read. This bit is not
masked except via the MASK bit.
Bit 5 - TCRIT - This bit is set to ‘1’ if any bit in the Tcrit Status Register is set. This bit is automatically
cleared when the Tcrit Status Register is read and the bits are cleared.
Bit 4 - GPIO (EMC2103-2 only) - This bit is set to ‘1’ if any bit in the GPIO Status Register is set. This
bit is automatically cleared when the GPIO Status Register is read.
Bit 3 - FAN - This bit is set to ‘1’ if any bit in the Fan Status Register is set. This bit is automatically
cleared when the Fan Status Register is read and the bits are cleared.
Bit 2 - HIGH - This bit is set to ‘1’ if any bit in the High Status Register is set. This bit is automatically
cleared when the High Status Register is read and the bits are cleared.
Bit 1- LOW - This bit is set to ‘1’ if any bit in the Low Status Register is set. This bit is automatically
cleared when the Low Status Register is read and the bits are cleared.
Bit 0 - FAULT - This bit is set to ‘1’ if any bit in the Diode Fault Register is set. This bit is automatically
cleared when the Diode Fault Register is read and the bits are cleared.
Table 6.18 Conversion Rate
CONV[1:0]
CONVERSION RATE
10
00
1 / sec
01
2 / sec
1
0
4 / sec (default)
1
Continuous
Table 6.19 Interrupt Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
23h
R-C
Interrupt
Status
Register
EEP
ROM
-
TCRIT
GPIO
FAN
HIGH
LOW
FAULT
00h
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