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参数资料
| 型号： | EP20K100BC484-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA484 |
| 文件页数： | 40/68页 |
| 文件大小： | 975K |
| 代理商： | EP20K100BC484-2 |
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45
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
mode. Refer to “Analog Comparator” on page 227 for details on how to configure the Analog
Comparator.
8.7.3
Brown-out Detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-
nificantly to the total current consumption. Refer to “Brown-out Detection” on page 48 for details
on how to configure the Brown-out Detector.
8.7.4
Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-
age Reference” on page 50 for details on the start-up time.
8.7.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to “Watchdog Timer” on page 52 for details on how to configure the Watchdog Timer.
8.7.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section “I/O-Ports” on page 62 for details on which pins are enabled. If the
input buffer is enabled and the input signal is left floating or have an analog signal level close to
V
CC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to “Digital Input Disable Register 1– DIDR1” and “Digital Input Disable Register 0
8.7.7
On-chip Debug System
If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the
main clock source is enabled, and hence, always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
相关PDF资料 |
PDF描述 |
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| EP20K100BC484-3 | LOADABLE PLD, PBGA484 |
| EP20K100BI484-1 | LOADABLE PLD, PBGA484 |
| EP20K100BI484-2 | LOADABLE PLD, PBGA484 |
| EP20K100BI484-3 | LOADABLE PLD, PBGA484 |
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相关代理商/技术参数 |
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| EP20K100BI356-1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K100BI356-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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| EP20K100BI356-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100BI356-3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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