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| 型号： | EP20K100EFI784-1 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA784 |
| 文件页数： | 10/65页 |
| 文件大小： | 781K |
| 代理商： | EP20K100EFI784-1 |
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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Normal Mode
The normal mode is suitable for general logic applications, combinatorial
functions, or wide decoding functions that can take advantage of a
cascade chain. In normal mode, four data inputs from the LAB local
interconnect and the carry-in are inputs to a 4-input LUT. The Quartus
Compiler automatically selects the carry-in or the DATA3 signal as one of
the inputs to the LUT. The LUT output can be combined with the
cascade-in signal to form a cascade chain through the cascade-out signal.
LEs in normal mode support packed registers.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, accumulators, and
comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT
computes a 3-input function; the other generates a carry output. As shown
in Figure 8, the first LUT uses the carry-in signal and two data inputs from
the LAB local interconnect to generate a combinatorial or registered
output. For example, when implementing an adder, this output is the sum
of three signals: DATA1, DATA2, and carry-in. The second LUT uses the
same three signals to generate a carry-out signal, thereby creating a carry
chain. The arithmetic mode also supports simultaneous use of the cascade
chain. LEs in arithmetic mode can drive out registered and unregistered
versions of the LUT output.
The Quartus software implements parameterized functions that use the
arithmetic mode automatically where appropriate; the designer does not
need to specify how the carry chain will be used.
Counter Mode
The counter mode offers clock enable, counter enable, synchronous
up/down control, synchronous clear, and synchronous load options. The
counter enable and synchronous up/down control signals are generated
from the data inputs of the LAB local interconnect. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. Consequently, if any of the LEs in an LAB use
counter mode, other LEs in that LAB must be used as part of the same
counter or be used for a combinatorial function. The Quartus software
automatically places any registers that are not used by the counter into
other LABs.
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相关代理商/技术参数 |
参数描述 |
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| EP20K100EQC208-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EQC208-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQC208-1X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EQC208-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EQC208-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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