参数资料
型号: EP20K100EQC240-3N
厂商: Altera
文件页数: 27/117页
文件大小: 0K
描述: IC APEX 20KE FPGA 100K 240-PQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 24
系列: APEX-20K®
LAB/CLB数: 416
逻辑元件/单元数: 4160
RAM 位总计: 53248
输入/输出数: 183
门数: 263000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 240-BFQFP
供应商设备封装: 240-PQFP(32x32)
Altera Corporation
17
APEX 20K Programmable Logic Device Family Data Sheet
LE Operating Modes
The APEX 20K LE can operate in one of the following three modes:
Normal mode
Arithmetic mode
Counter mode
Each mode uses LE resources differently. In each mode, seven available
inputs to the LE—the four data inputs from the LAB local interconnect,
the feedback from the programmable register, and the carry-in and
cascade-in from the previous LE—are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset, asynchronous load,
synchronous clear, synchronous load, and clock enable control for the
register. These LAB-wide signals are available in all LE modes.
The Quartus II software, in conjunction with parameterized functions
such as LPM and DesignWare functions, automatically chooses the
appropriate mode for common functions such as counters, adders, and
multipliers. If required, the designer can also create special-purpose
functions that specify which LE operating mode to use for optimal
performance. Figure 8 shows the LE operating modes.
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