参数资料
| 型号： | EP20K100EQC240-3N |
| 厂商： | Altera |
| 文件页数： | 41/117页 |
| 文件大小： | 0K |
| 描述： | IC APEX 20KE FPGA 100K 240-PQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 24 |
| 系列： | APEX-20K® |
| LAB/CLB数： | 416 |
| 逻辑元件/单元数： | 4160 |
| RAM 位总计： | 53248 |
| 输入/输出数： | 183 |
| 门数： | 263000 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 240-BFQFP |
| 供应商设备封装： | 240-PQFP（32x32） |
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Altera Corporation
3
APEX 20K Programmable Logic Device Family Data Sheet
■
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
–
Built-in low-skew clock tree
–
Up to eight global clock signals
–
ClockLock feature reducing clock delay and skew
–
ClockBoost feature providing clock multiplication and division
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ClockShiftTM programmable clock phase and delay shifting
■
Powerful I/O features
–
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
–
Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
–
Bidirectional I/O performance (tCO + tSU) up to 250 MHz
–
LVDS performance up to 840 Mbits per channel
–
Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
–
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
–
Programmable clamp to VCCIO
–
Individual tri-state output enable control for each pin
–
Programmable output slew-rate control to reduce switching
noise
–
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
–
Pull-up on I/O pins before and during configuration
■
Advanced interconnect structure
–
Four-level hierarchical FastTrack Interconnect structure
providing fast, predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
■
Advanced packaging options
–
Available in a variety of packages with 144 to 1,020 pins (see
–
FineLine BGA packages maximize board space efficiency
■
Advanced software support
–
Software design support and automatic place-and-route
provided by the Altera Quartus II development system for
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100EQC240-3 | IC APEX 20KE FPGA 100K 240-PQFP |
| EP1K50FC484-1N | IC ACEX 1K FPGA 50K 484-FBGA |
| EP1K50FC484-1 | IC ACEX 1K FPGA 50K 484-FBGA |
| HMC43DRXN | CONN EDGECARD 86POS DIP .100 SLD |
| HMC43DRXH | CONN EDGECARD 86POS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EQI208-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQI208-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQI208-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQI240-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQI240-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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