参数资料
型号: EP20K100EQC240-3N
厂商: Altera
文件页数: 58/117页
文件大小: 0K
描述: IC APEX 20KE FPGA 100K 240-PQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 24
系列: APEX-20K®
LAB/CLB数: 416
逻辑元件/单元数: 4160
RAM 位总计: 53248
输入/输出数: 183
门数: 263000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 240-BFQFP
供应商设备封装: 240-PQFP(32x32)
Altera Corporation
45
APEX 20K Programmable Logic Device Family Data Sheet
Figure 29. APEX 20KE I/O Banks
Notes to Figure 29:
(1)
For more information on placing I/O pins in LVDS blocks, refer to the Guidelines for
Using LVDS Blocks section in Application Note 120 (Using LVDS in APEX 20KE
Devices).
(2)
If the LVDS input and output blocks are not used for LVDS, they can support all of
the I/O standards and can be used as input, output, or bidirectional pins with
VCCIO set to 3.3 V, 2.5 V, or 1.8 V.
Power Sequencing & Hot Socketing
Because APEX 20K and APEX 20KE devices can be used in a mixed-
voltage environment, they have been designed specifically to tolerate any
possible power-up sequence. Therefore, the VCCIO and VCCINT power
supplies may be powered in any order.
f For more information, please refer to the “Power Sequencing
Considerations” section in the Configuring APEX 20KE & APEX 20KC
Devices chapter of the Configuration Devices Handbook.
Signals can be driven into APEX 20K devices before and during power-up
without damaging the device. In addition, APEX 20K devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX 20K and APEX 20KE devices operate as
specified by the user.
LVDS/LVPECL
Input
Block (2)
(1)
LVDS/LVPECL
Output
Block (2)
(1)
Regular I/O Blocks Support
LVTTL
LVCMOS
2.5 V
1.8 V
3.3 V PCI
LVPECL
HSTL Class I
GTL+
SSTL-2 Class I and II
SSTL-3 Class I and II
CTT
AGP
Individual
Power Bus
I/O Bank 8
I/O Bank 1
I/O Bank 2
I/O Bank 3
I/O Bank 4
I/O Bank 5
I/O Bank 6
I/O Bank 7
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