参数资料
| 型号： | EP3SL340F1760C3N |
| 厂商： | Altera |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX III L 340K 1760-FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® III |
| LAB/CLB数： | 13500 |
| 逻辑元件/单元数： | 337500 |
| RAM 位总计： | 18822144 |
| 输入/输出数： | 1120 |
| 电源电压： | 0.86 V ~ 1.15 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 1760-BBGA，FCBGA |
| 供应商设备封装： | 1760-FCBGA |
Chapter 1: Stratix III Device Family Overview
1–3
Features Summary
Table 1–1 lists the Stratix III FPGA family features.
The Stratix III logic family (L) offers balanced logic, memory, and multipliers to
address a wide range of applications, while the enhanced family (E) offers more
memory and multipliers per logic and is ideal for wireless, medical imaging, and
military applications.
Stratix III devices are available in space-saving FineLine BGA (FBGA) packages (refer
Table 1–1. FPGA Family Features for Stratix III Devices
Device/
Feature
ALMs
LEs
M9K
Blocks
M144K
Blocks
MLAB
Blocks
Total
Embedded
RAM Kbits
MLAB
RAM
Kbits
Total
RAM
Kbits(2)
18×18-bit
Multipliers
(FIR Mode)
PLLs
Stratix III
Logic
Family
EP3SL50
19K
47.5K
108
6
950
1,836
297
2,133
216
4
EP3SL70
27K
67.5K
150
6
1,350
2,214
422
2,636
288
4
EP3SL110
43K
107.5K
275
12
2,150
4,203
672
4,875
288
8
EP3SL150
57K
142.5K
355
16
2,850
5,499
891
6,390
384
8
EP3SL200
80K
200K
468
36
4,000
9,396
1,250
10,646
576
12
EP3SL340
135K
337.5K
1,040
48
6,750
16,272
2,109
18,381
576
12
Stratix III
Enhanced
Family
EP3SE50
19K
47.5K
400
12
950
5,328
297
5,625
384
4
EP3SE80
32K
80K
495
12
1,600
6,183
500
6,683
672
8
EP3SE110
43K
107.5K
639
16
2,150
8,055
672
8,727
896
8
EP3SE260
102K
255K
864
48
5,100
14,688
1,594
16,282
768
12
Notes to Table 1–1:
(1) MLAB ROM mode supports twice the number of MLAB RAM Kbits.
(2) For total ROM Kbits, use this equation to calculate:
Total ROM Kbits = Total Embedded RAM Kbits + [(# of MLAB blocks × 640)/1024]
(3) The availability of the PLLs shown in this column is based on the device with the largest package. Refer to the Clock Networks and PLLs in Stratix
III Devices chapter in volume 1 of the Stratix III Device Handbook for the availability of the PLLs for each device.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP3SL340F1760C3NES | 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA |
| EP3SL340F1760C4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4L | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4LN | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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