参数资料
型号: EP3SL340F1760C3N
厂商: Altera
文件页数: 13/16页
文件大小: 0K
描述: IC STRATIX III L 340K 1760-FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 3
系列: Stratix® III
LAB/CLB数: 13500
逻辑元件/单元数: 337500
RAM 位总计: 18822144
输入/输出数: 1120
电源电压: 0.86 V ~ 1.15 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 1760-BBGA,FCBGA
供应商设备封装: 1760-FCBGA
1–6
Chapter 1: Stratix III Device Family Overview
Architecture Features
Architecture Features
The following section describes the various features of the Stratix III family FPGAs.
Logic Array Blocks and Adaptive Logic Modules
The Logic Array Block (LAB) is composed of basic building blocks known as
Adaptive Logic Modules (ALMs) that can be configured to implement logic,
arithmetic, and register functions. Each LAB consists of ten ALMs, carry chains,
shared arithmetic chains, LAB control signals, local interconnect, and register chain
connection lines. ALMs are part of a unique, innovative logic structure that delivers
faster performance, minimizes area, and reduces power consumption. ALMs expand
the traditional 4-input look-up table architecture to 7 inputs, increasing performance
by reducing LEs, logic levels, and associated routing. In addition, ALMs maximize
DSP performance with dedicated functionality to efficiently implement adder trees
and other complex arithmetic functions. The Quartus II Compiler places associated
logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
The Stratix III LAB has a new derivative called Memory LAB (or MLAB), which adds
SRAM memory capability to the LAB. MLAB is a superset of the LAB and includes all
LAB features. MLABs support a maximum of 320 bits of simple dual-port Static
Random Access Memory (SRAM). Each ALM in an MLAB can be configured as a
16×2 block, resulting in a configuration of 16×20 simple dual port SRAM block. MLAB
and LAB blocks always co-exist as pairs in all Stratix III families, allowing up to 50%
of the logic (LABs) to be traded for memory (MLABs).
f For more information about LABs and ALMs, refer to the Logic Array Blocks and
f For more information about MLAB modes, features and design considerations, refer
EP3SE260
Commercial
–2, –3, –4,
–4L
–2,– 3, –4,
–4L
–2, –3, –4,
–4L
Industrial (1)
–3, –4, –4L
–3, –4,–4L
Note to Table 1–5:
(1) For EP3SL340, EP3SL200, and EP3SE260 devices, the industrial junction temperature range for –4L is 0–100°C, regardless of supply voltage.
Table 1–5. Speed Grades for Stratix III Devices (Part 2 of 2)
Device
Temperature
Grade
484 -Pin
FineLine
BGA
780-Pin
FineLine
BGA
780-Pin
Hybrid
FineLine
BGA
1152-Pin
FineLine
BGA
1152-Pin
Hybrid
FineLine
BGA
1517-Pin
FineLine
BGA
1760-Pin
FineLine
BGA
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EP3SL340F1760C3NES 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA
EP3SL340F1760C4 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP3SL340F1760C4L 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP3SL340F1760C4LN 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP3SL340F1760C4N 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256