参数资料
| 型号： | EP3SL340F1760C3N |
| 厂商： | Altera |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX III L 340K 1760-FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® III |
| LAB/CLB数： | 13500 |
| 逻辑元件/单元数： | 337500 |
| RAM 位总计： | 18822144 |
| 输入/输出数： | 1120 |
| 电源电压： | 0.86 V ~ 1.15 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 1760-BBGA，FCBGA |
| 供应商设备封装： | 1760-FCBGA |
Chapter 1: Stratix III Device Family Overview
1–9
Architecture Features
f For more information, refer to the Clock Networks and PLLs in Stratix III Devices
chapter.
I/O Banks and I/O Structure
Stratix III devices contain up to 24 modular I/O banks, each of which contains 24, 32,
36, 40, or 48 I/Os. This modular bank structure improves pin efficiency and eases
device migration. The I/O banks contain circuitry to support external memory
interfaces at speeds up to 533 MHz and high-speed differential I/O interfaces meeting
up to 1.6 Gbps performance. It also supports high-speed differential inputs and
outputs running at speeds up to 800 MHz.
Stratix III devices support a wide range of industry I/O standards, including
single-ended, voltage referenced single-ended, and differential I/O standards. The
Stratix III I/O supports programmable bus hold, programmable pull-up resistor,
programmable slew rate, programmable drive strength, programmable output delay
control, and open-drain output. Stratix III devices also support on-chip series (RS) and
on-chip parallel (RT) termination with auto calibration for single-ended I/O standards
and on-chip differential termination (RD) for LVDS I/O standards on Left/Right I/O
banks. Dynamic OCT is also supported on bi-directional I/O pins in all I/O banks.
f For more information, refer to the Stratix III Device I/O Features chapter.
External Memory Interfaces
The Stratix III I/O structure has been completely redesigned to provide flexibility and
enable high-performance support for existing and emerging external memory
standards such as DDR, DDR2, DDR3, QDR II, QDR II+, and RLDRAM II at
frequencies of up to 533 MHz.
Packed with features such as dynamic on-chip termination, trace mismatch
compensation, read/write leveling, half-rate registers, and 4-to 36-bit programmable
DQ group widths, Stratix III I/Os supply the built-in functionality required for rapid
and robust implementation of external memory interfaces. Double data-rate support
is found on all sides of the Stratix III device. Stratix III devices provide an efficient
architecture to quickly and easily fit wide external memory interfaces exactly where
you want them.
A self-calibrating soft IP core (ALTMEMPHY), optimized to take advantage of the
Stratix III device I/O, along with the Quartus II timing analysis tool (TimeQuest),
provide the total solution for the highest reliable frequency of operation across
process voltage and temperature.
f For more information about external memory interfaces, refer to the External Memory
Interfaces in Stratix III Devices chapter.
High-Speed Differential I/O Interfaces with DPA
Stratix III devices contain dedicated circuitry for supporting differential standards at
speeds up to 1.6 Gbps. The high-speed differential I/O circuitry supports the
following high-speed I/O interconnect standards and applications: Utopia IV, SPI-4.2,
SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. Stratix III devices support 2×,
4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP3SL340F1760C3NES | 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA |
| EP3SL340F1760C4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4L | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4LN | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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