参数资料
| 型号： | EP3SL340F1760C3N |
| 厂商： | Altera |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX III L 340K 1760-FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® III |
| LAB/CLB数： | 13500 |
| 逻辑元件/单元数： | 337500 |
| RAM 位总计： | 18822144 |
| 输入/输出数： | 1120 |
| 电源电压： | 0.86 V ~ 1.15 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 1760-BBGA，FCBGA |
| 供应商设备封装： | 1760-FCBGA |
1–12
Chapter 1: Stratix III Device Family Overview
Architecture Features
The design security feature is available when configuring Stratix III FPGAs using the
fast passive parallel (FPP) configuration mode with an external host (such as a MAX II
device or microprocessor), or when using fast active serial (AS) or passive serial (PS)
configuration schemes.
f For more information about the design security feature, refer to the Design Security in
Stratix III Devices chapter.
SEU Mitigation
Stratix III devices have built-in error detection circuitry to detect data corruption due
to soft errors in the configuration random-access memory (CRAM) cells. This feature
allows all CRAM contents to be read and verified continuously during user mode
operation to match a configuration-computed CRC value. The enhanced CRC circuit
and frame-based configuration architecture allows detection and location of multiple,
single, and adjacent bit errors which, in conjunction with a soft circuit supplied as a
reference design, allows don’t-care soft errors in the CRAM to be ignored during
device operation. This provides a steep decrease in the effective soft error rate,
increasing system reliability.
On-chip memory block SEU mitigation is also offered using the ninth bit and a
configurable megafunction in the Quartus II software for MLAB and M9K blocks
while the M144K memory blocks have built-in error correction code (ECC) circuitry.
f For more information about the dedicated error detection circuitry, refer to the SEU
Mitigation in Stratix III Devices chapter.
Programmable Power
Stratix III delivers Programmable Power, the only FPGA with user programmable
power options balancing today’s power and performance requirements. Stratix III
devices utilize the most advanced power-saving techniques, including a variety of
process, circuit, and architecture optimizations and innovations. In addition, user
controllable power reduction techniques provide an optimal balance of performance
and power reduction specific for each design configured into the Stratix III FPGA. The
Quartus II software (starting from version 6.1) automatically optimizes designs to
meet the performance goals while simultaneously leveraging the programmable
power-saving options available in the Stratix III FPGA without the need for any
changes to the design flow.
f For more information about Programmable Power in Stratix III devices, refer to the
following documents:
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP3SL340F1760C3NES | 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA |
| EP3SL340F1760C4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4L | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4LN | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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