参数资料
| 型号： | EP3SL340F1760C3N |
| 厂商： | Altera |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX III L 340K 1760-FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® III |
| LAB/CLB数： | 13500 |
| 逻辑元件/单元数： | 337500 |
| RAM 位总计： | 18822144 |
| 输入/输出数： | 1120 |
| 电源电压： | 0.86 V ~ 1.15 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 1760-BBGA，FCBGA |
| 供应商设备封装： | 1760-FCBGA |
1–4
Chapter 1: Stratix III Device Family Overview
Features Summary
Table 1–2 lists the Stratix III FPGA package options and I/O pin counts.
All Stratix III devices support vertical migration within the same package (for
example, you can migrate between the EP3SL50 and EP3SL70 devices in the 780-pin
FineLine BGA package). Vertical migration allows you to migrate to devices whose
dedicated pins, configuration pins, and power pins are the same for a given package
across device densities.
To ensure that a board layout supports migratable densities within one package
offering, enable the applicable vertical migration path within the Quartus II
software. On the Assignments menu, point to Device and click Migration Devices.
You can migrate from the L family to the E family without increasing the number of
LEs available. This minimizes the cost of vertical migration.
Table 1–3 lists the Stratix III FineLine BGA (FBGA) package sizes.
Table 1–2. Package Options and I/O Pin Counts (Note 1)
Device
484-Pin
FineLine
BGA (2)
780-Pin
FineLine
BGA (2)
1152-Pin
FineLine
BGA (2)
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
EP3SL50
296
488
—
EP3SL70
296
488
—
EP3SL110
—
488
744
—
EP3SL150
—
488
744
—
EP3SL200
—
488 (5)
744
976
—
EP3SL340
—
744 (4)
976
1,120
EP3SE50
296
488
—
EP3SE80
—
488
744
—
EP3SE110
—
488
744
—
EP3SE260
—
488 (5)
744
976
—
Notes to Table 1–2:
(1) The arrows indicate vertical migration.
(2) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n,
CLK10p,
and CLK10n) that can be used for data inputs.
(3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p,
CLK8n, CLK10p,
and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp,
PLL
_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp,
and PLL_R1_CLKn) that can be used for data inputs.
(4) The EP3SL340 FPGA is offered only in the H1152 package, but not offered in the F1152 package.
(5) The EP3SE260 and EP3SL200 FPGAs are offered only in the H780 package, but not offered in the F780 package.
Table 1–3. FineLine BGA Package Sizes
Dimension
484 Pin
780 Pin
1152 Pin
1517 Pin
1760 Pin
Pitch (mm)
1.00
Area (mm2)
529
841
1,225
1,600
1,849
Length/Width (mm
mm)
23/23
29/29
35/35
40/40
43/43
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP3SL340F1760C3NES | 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA |
| EP3SL340F1760C4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4L | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4LN | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP3SL340F1760C4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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