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参数资料
| 型号： | EPF10K100E |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10KE嵌入式可编程逻辑系列） |
| 文件页数： | 5/31页 |
| 文件大小： | 299K |
| 代理商： | EPF10K100E |
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Altera Corporation
873
AN 91: Understanding FLEX 10K Timing
1
For more information, see
“Timing Model vs.
MAX+PLUS II Timing Analyzer” on page 891
.
t
LEPERIPH
Peripheral bus delay. Routing delay for an LE or IOE
driving a control signal of an IOE via the peripheral
control bus. The value shown in the
Programmable Logic Family Data Sheet
Embedded Programmable Logic Device Family Data Sheet
the longest delay possible for an LE with a fan-out of four
loads. However, the value generated by the
MAX+PLUS II Timing Analyzer is more accurate because
it considers fan-out and the relative locations of the
source and destination in the design.
FLEX 10K Embedded
and
FLEX 10KE
is
1
For more information, see
“Timing Model vs.
MAX+PLUS II Timing Analyzer” on page 891
.
t
LABCARRY
Carry chain delay to a different LAB. The routing delay
for a carry-out signal of an LE driving the carry-in signal
of an LE in a different LAB in the same row. A carry chain
longer than one LAB skips either from one even-
numbered LAB to another even-numbered LAB, or from
one odd-numbered LAB to another odd-numbered LAB.
t
LABCASC
Cascade chain delay to a different LAB. The routing
delay for a cascade-out signal of an LE driving the
cascade-in signal of an LE in a different LAB in the same
row. A cascade chain longer than one LAB skips either
from one even-numbered LAB to another even-
numbered LAB, or from one odd-numbered LAB to
another odd-numbered LAB.
t
DIN2IOE
Delay from dedicated input pin to IOE control input. The
time required for a signal on a dedicated input pin to
reach an IOE control input.
t
DIN2LE
Delay from dedicated input pin to LE or EAB control
input. The time required for a signal on a dedicated input
pin to reach an LE or EAB control input.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K100EBC356-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EBC356-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-1X | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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