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参数资料
| 型号： | EPF10K100E |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10KE嵌入式可编程逻辑系列） |
| 文件页数： | 6/31页 |
| 文件大小： | 299K |
| 代理商： | EPF10K100E |
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874
Altera Corporation
AN 91: Understanding FLEX 10K Timing
t
DIN2DATA
Delay from dedicated input pin to LE or EAB data input.
The time required for a signal on a dedicated input pin to
reach an LE or EAB data input. The value shown in the
FLEX 10K Embedded Programmable Logic Family Data Sheet
and
FLEX 10KE Embedded Programmable Logic Device
Family Data Sheet
is the longest delay possible for a pin
with a fan-out of four loads. However, the value
generated by the MAX+PLUS II Timing Analyzer is more
accurate because it considers fan-out and the relative
locations of the source and destination in the design.
1
For more information, see
“Timing Model vs.
MAX+PLUS II Timing Analyzer” on page 891
.
t
DCLK2IOE
Delay from dedicated clock pin to IOE clock. The time
required for a signal on a dedicated clock pin to reach an
IOE clock input.
t
DCLK2LE
Delay from dedicated clock pin to LE or EAB clock. The
time required for a signal on a dedicated clock pin to
reach an LE or EAB clock input.
Logic Element Timing Microparameters
The following list describes the LE timing microparameters for the
FLEX 10K device family.
t
LUT
Look-up table (LUT) delay. The delay incurred by
generating an LUT output from an LAB local
interconnect signal.
t
RLUT
LUT using LE feedback delay. The time required for the
output of an LE register to be fed back and used to
generate the LUT output in the same LE.
t
CLUT
Carry-chain LUT delay. The delay incurred by a carry
chain signal used to generate the LUT output.
t
PACKED
Data-in to packed register delay. The delay incurred by
routing an LAB local interconnect signal around the
LUT to the LE register data input.
t
C
Register control delay. The time required for a signal to
be routed to the clock, preset, or clear input of an LE
register.
相关PDF资料 |
PDF描述 |
|---|---|
| EPF10K70 | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K10A | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K250A | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K30 | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K200E | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K100EBC356-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EBC356-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-1X | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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