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参数资料
| 型号： | EPF10K100E |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10KE嵌入式可编程逻辑系列） |
| 文件页数： | 7/31页 |
| 文件大小： | 299K |
| 代理商： | EPF10K100E |
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Altera Corporation
875
AN 91: Understanding FLEX 10K Timing
t
EN
LE register enable delay. The time required for a signal to
be routed to the enable input of an LE register.
t
CGENR
Carry-out generation using LE feedback delay. The time
required for the output of an LE register to be fed back
and used to generate the carry-out signal in the same LE.
t
CGEN
Carry-out generation delay. The delay incurred by
generating a carry-out signal from an LAB local
interconnect signal.
t
CICO
Carry-in to carry-out delay. The delay incurred by
generating a carry-out signal that uses the carry-in signal
from the previous LE.
t
CO
LE clock-to-output delay. The delay from the rising edge
of the LE register’s clock to the time the data appears at
the register output.
t
COMB
Combinatorial output delay. The time required for a
combinatorial signal to bypass the LE register and
become the output of the LE.
t
SU
LE register setup time for data and enable signals before
clock. The minimum time a signal must be stable at the
LE register’s data and enable inputs before the register
clock’s rising edge to ensure that the register correctly
stores the input data. The
t
SU
parameter is also the
minimum recovery time between deasserting the clear
or preset and the rising edge of the clock.
t
H
LE register hold time for data and enable signals after
clock. The minimum time a signal must be stable at the
LE register’s data and enable inputs after the register
clock’s rising edge to ensure that the register correctly
stores the input data.
t
PRE
LE register preset delay. The delay from the assertion of
the LE register’s asynchronous preset input to the time
the register output stabilizes at a logic high.
t
CLR
LE register clear delay. The delay from the assertion of
the LE register’s asynchronous clear input to the time the
register output stabilizes at a logic low.
t
CASC
Cascade chain delay. The time required for a cascade-out
signal to be routed to the next LE in the same LAB. This
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K100EBC356-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EBC356-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-1X | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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