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参数资料
| 型号： | EPF10K100E |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10KE嵌入式可编程逻辑系列） |
| 文件页数： | 9/31页 |
| 文件大小： | 299K |
| 代理商： | EPF10K100E |
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Altera Corporation
877
AN 91: Understanding FLEX 10K Timing
t
EABCH
Clock high time. The minimum time an EAB clock signal
must remain at a logic high for proper clocking of the
EAB registers.
t
EABCL
Clock low time. The minimum time an EAB clock signal
must remain at a logic low for proper clocking of the
EAB registers.
t
AA
Address access delay. The delay from an EAB RAM
address input change to an EAB RAM data output
change.
t
DD
Data-in to data-out valid delay. The time required for
data at the EAB RAM data input to propagate to the EAB
RAM data output during a write cycle.
t
WP
Write pulse width. The minimum time
WE
must be held at
a logic high to ensure that the EAB RAM correctly stores
the input data.
t
WDSU
Data setup time before falling edge of write pulse. The
minimum time a signal must be stable at the EAB RAM
data input before the falling edge of
WE
to ensure that the
RAM correctly stores the input data.
t
WDH
Data hold time after falling edge of write pulse. The
minimum time a signal must be stable at the EAB RAM
data input after the falling edge of
WE
to ensure that the
RAM correctly stores the input data.
t
WASU
Address setup time before rising edge of write pulse. The
minimum time that a signal is required to be stable at the
EAB RAM address input before the rising edge of
WE
to
ensure that the RAM correctly stores the input data.
t
WAH
Address hold time after falling edge of write pulse. The
minimum time that a signal is required to be stable at the
EAB RAM address input after the falling edge of
WE
to
ensure that the RAM correctly stores the input data.
t
WO
Write enable to data output valid delay. The delay from
the rising edge of
WE
to data, which was just written to
RAM, appearing at the EAB RAM data output.
t
EABOUT
Data-out delay. The time required for the output of an
EAB to reach a row or column channel of the FastTrack
Interconnect.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K100EBC356-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EBC356-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-1X | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EBC356-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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