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参数资料
| 型号： | EPF10K70 |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10K嵌入式可编程逻辑系列） |
| 文件页数： | 10/31页 |
| 文件大小： | 299K |
| 代理商： | EPF10K70 |
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878
Altera Corporation
AN 91: Understanding FLEX 10K Timing
Internal EAB
Timing
Macropara-
meters
Internal EAB timing macroparameters are combinations of FLEX 10K
internal EAB timing microparameters. These macroparameters cannot be
measured explicitly. The following list defines the internal EAB timing
macroparameters for the FLEX 10K device family.
t
EABAA
EAB address access delay. The delay from an EAB
address input change to an EAB data output change.
t
EABRCCOMB
EAB asynchronous read cycle time. The minimum time
required to complete an asynchronous read cycle.
t
EABRCREG
EAB synchronous read cycle time. The minimum time
required to complete a synchronous read cycle.
t
EABWP
EAB write pulse width. The minimum time the EAB
WE
input must be held at a logic high to ensure that the EAB
RAM correctly stores the input data.
t
EABWCCOMB
EAB asynchronous write cycle time. The minimum time
required to complete an asynchronous write cycle.
t
EABWCREG
EAB synchronous write cycle time. The minimum time
required to complete a synchronous write cycle.
t
EABDD
EAB data-in to data-out valid delay. The amount of time
required for data at the EAB data input to propagate
through the EAB RAM to the EAB data output during a
write cycle.
t
EABDATACO
EAB clock-to-output delay when using output registers.
The delay from the rising edge of the EAB output register
clock input to the time the data appears at the EAB data
output.
t
EABDATASU
EAB data/address setup time before clock when using
input register. The minimum time a signal must be stable
at the EAB data/address input before the EAB input
register clock’s rising edge to ensure that the input
register correctly stores the input data.
t
EABDATAH
EAB data/address hold time after clock when using input
register. The minimum time a signal must be stable at the
EAB data/address input after the EAB input register
clock’s rising edge to ensure that the input register
correctly stores the input data.
相关PDF资料 |
PDF描述 |
|---|---|
| EPF10K10A | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K250A | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K30 | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K200E | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
| EPF10K30E | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K70RC240-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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