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| 型号： | EPF10K70 |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10K嵌入式可编程逻辑系列） |
| 文件页数： | 2/31页 |
| 文件大小： | 299K |
| 代理商： | EPF10K70 |
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870
Altera Corporation
AN 91: Understanding FLEX 10K Timing
t
IOFD
IOE register feedback delay. The time required for the
output of an IOE register to reach a row or column
channel of the FastTrack Interconnect.
t
INCOMB
IOE input pad and buffer to FastTrack Interconnect delay.
The time required for a signal on an I/O pin, used as an
input, to reach a row or column channel of the FastTrack
Interconnect.
t
INREG
IOE input pad and buffer to IOE register delay. The time
required for a signal on an I/O pin, used as an input, to
reach an IOE register data input.
t
IOCO
I/O register clock-to-output delay. The delay from the
rising edge of the I/O register’s clock to the time the data
appears at the register output.
t
IOCOMB
I/O register bypass delay. The delay for a combinatorial
signal to bypass the I/O register.
t
IOSU
I/O register setup time for data and enable signals before
clock. The minimum time a signal must be stable at the
I/O register’s data and enable inputs before the register
clock’s rising edge to ensure that the register correctly
stores the input data.
t
IOSU
is also the minimum recovery
time between deassertions of clear and the rising edge of
the clock.
t
IOH
I/O register hold time for data and enable signals after
clock. The minimum time a signal must be stable at the
I/O register’s data and enable inputs after the register
clock’s rising edge to ensure that the register correctly
stores the input data.
t
IOCLR
I/O register clear delay. The delay from the time the I/O
register’s asynchronous clear input is asserted to the time
the register output stabilizes at a logic low.
t
OD1
Output buffer and pad delay with the slow slew rate
logic option turned off and V
CCIO
= V
CCINT
.
t
OD2
Output buffer and pad delay with the slow slew rate
logic option turned off and V
CCIO
= low voltage.
t
OD3
Output buffer and pad delay with the slow slew rate
logic option turned on.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K70RC240-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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