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参数资料
| 型号： | EPF10K70 |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10K嵌入式可编程逻辑系列） |
| 文件页数： | 3/31页 |
| 文件大小： | 299K |
| 代理商： | EPF10K70 |
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Altera Corporation
871
AN 91: Understanding FLEX 10K Timing
t
XZ
Output buffer disable delay. The delay required for high
impedance to appear at the output pin after the tri-state
buffer’s enable control is disabled.
t
ZX1
Output buffer enable delay with the slow slew rate logic
option turned off and V
CCIO
= V
CCINT
. The delay
required for the output signal to appear at the output
pin after the tri-state buffer’s enable control is enabled.
t
ZX2
Output buffer enable delay with the slow slew rate logic
option turned off and V
CCIO
= low voltage. The delay
required for the output signal to appear at the output
pin after the tri-state buffer’s enable control is enabled.
t
ZX3
Output buffer enable delay with the slow slew rate logic
option turned on. The delay required for the output
signal to appear at the output pin after the tri-state
buffer’s enable control is enabled.
Interconnect Timing Microparameters
The following list describes the routing timing microparameters for the
FLEX 10K device family.
t
SAMELAB
Logic element (LE) to LE in same logic array block (LAB)
delay. The delay incurred by a signal routed between LEs
in the same LAB.
t
SAMEROW
FastTrack Interconnect same row delay. The delay
incurred by a row IOE, LE, or embedded array block
(EAB) driving a row IOE, LE or EAB in the same row. The
t
SAMEROW
delay is a function of fan-out and the distance
between the source and destination. The value shown in
the
FLEX 10K Embedded Programmable Logic Family Data
Sheet
and
FLEX 10KE Embedded Programmable Logic Device
Family Data Sheet
is the longest delay possible for an LE
with a fan-out of four loads. However, the value
generated by the MAX+PLUS II Timing Analyzer is more
accurate because it considers fan-out and the relative
locations of the source and destination in the design.
1
For more information, see
“Timing Model vs.
MAX+PLUS II Timing Analyzer” on page 891
.
相关PDF资料 |
PDF描述 |
|---|---|
| EPF10K10A | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K250A | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K30 | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| EPF10K200E | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
| EPF10K30E | Embedded Programmable Logic Family(FLEX10KE嵌入式可编程逻辑系列) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K70RC240-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K70RC240-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 468 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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