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参数资料
| 型号： | EPF6024A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 10/21页 |
| 文件大小： | 241K |
| 代理商： | EPF6024A |
928
Altera Corporation
AN 92: Understanding FLEX 6000 Timing
Calculating
Timing Delays
You can calculate approximate pin-to-pin timing delays for FLEX 6000
devices using the timing model shown in
Figure 1
along with the internal
timing parameters in the
FLEX 6000 Programmable Logic Device Family Data
Sheet
in this data book. Each external timing parameter is calculated from
a combination of internal timing parameters.
Figure 2
shows the FLEX 6000 device family external timing parameters.
For simplicity, the external parameters that contain output pin delays are
shown with FastFLEX I/O pins. A FastFLEX I/O pin is a row or column
output pin that receives its data signals from the adjacent local
interconnect driven by an adjacent LE. To calculate the routing delays for
pins that do not use the FastFLEX I/O feature, add the following delays:
I
Add a
t
ROW
delay for row output pins driven by non-adjacent LEs in
the same row. This delay also applies to column output pins driven
by non-adjacent LEs in the nearest row.
Add a
t
COL
+
t
ROW
delay for all other routing paths.
I
To calculate the delay for a signal that follows a different path, refer to the
timing model to determine which internal timing parameters to sum.
Figure 2. Logic Element External Timing Parameters (Part 1 of 4)
Combinatorial Delay
From Row I/O Inputs:
t
COMB
=
t
IN
+ t
ROW
+ t
LOCAL
+ t
DATA_TO_OUT
+ t
LOCAL
+ t
OD1
From Dedicated Inputs:
t
COMB
=
t
DIN_D
+ t
LOCAL
+ t
DATA_TO_OUT
+ t
LOCAL
+ t
OD1
Clock-to-Output Delay from a Global Clock to Any Output
t
CO
=
t
DIN_C
+ t
CO
+ t
REG_TO_OUT
+ t
LOCAL
+ t
OD1
Row or Column FastFLEX I/O
Combinatorial
Logic
Dedicated Input
Dedicated Clock
LE Register
Row or Column FastFLEX I/O
Row or Column FastFLEX I/O
Row I/O
Combinatorial
Logic
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6024ABC256-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-3N | 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz CMOS Technology 3.3V 256-Pin BGA 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz 0.42um Technology 3.3V 256-Pin BGA |
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