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参数资料
| 型号： | EPF6024A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 7/21页 |
| 文件大小： | 241K |
| 代理商： | EPF6024A |
Altera Corporation
925
AN 92: Understanding FLEX 6000 Timing
t
CL
Minimum LE register clock low time. The minimum
time that the register’s clock input must remain at a
stable logic low state before the rising edge of the
clock.
External Timing
Parameters
External timing parameters represent actual pin-to-pin timing
characteristics. Each external timing parameter consists of a combination
of internal delay elements. They are worst-case values, derived from
extensive performance measurements, and they are ensured by device
testing or characterization. All external timing parameters are shown in
bold type. For example,
t
1
is the AC operating specification. Other
external timing parameters can be estimated by using the timing model or
the equations in
“Calculating Timing Delays” on page 928
.
External Reference Timing Parameters
The following list describes the external reference timing parameters for
the FLEX 6000 device family:
t
1
This timing parameter shows the delay of a register-
to-register test pattern. There are 12 LEs including the
source and destination registers. The row and column
interconnects between the registers have various
lengths. This timing parameter is used to determine
the speed grade of FLEX 6000 devices.
External Timing Parameters
The following list describes the external timing parameters for the
FLEX 6000 device family.
t
INSU
Setup time with global clock into LE register on the
same row in column nearest to the I/O. The time
required for a signal to be stable at the input pin before
a rising edge is applied to the global clock pin to
ensure that the register correctly stores the input data.
The data input of the LE register is driven by an input
pin in the same row.
t
INH
Hold time with global clock from an I/O pin to any LE
register. The time required for a signal to be stable at
the input pin after a rising edge is applied to the global
clock pin to ensure that the register correctly stores the
input data. This parameter does not include the
optional increased input delay.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6024ABC256-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-3N | 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz CMOS Technology 3.3V 256-Pin BGA 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz 0.42um Technology 3.3V 256-Pin BGA |
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