- 您现在的位置：买卖IC网 > PDF目录362744 > EPF6024A (Altera Corporation) Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) PDF资料下载
参数资料
| 型号： | EPF6024A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 16/21页 |
| 文件大小： | 241K |
| 代理商： | EPF6024A |
934
Altera Corporation
AN 92: Understanding FLEX 6000 Timing
The MAX+PLUS II Report File for the circuit shown in
Figure 4
gives the
equations for
eq
, the output of the comparator:
eq
_LC3_B1 =
_EQ002C =
_EQ002
=
_LC3_B1;
LCELL( _EQ002C);
_EQ002 & CASCADE( _EQ001C);
a2 & a3 & b2 & b3
# a2 & !a3 & b2 & !b3
# !a2 & a3 & !b2 & b3
# !a2 & !a3 & !b2 & !b3;
LCELL( _EQ001C);
_EQ001;
a0 & a1 & b0 & b1
# a0 & !a1 & b0 & !b1
# !a0 & a1 & !b0 & b1
# !a0 & !a1 & !b0 & !b1;
=
_LC2_B1 =
_EQ001C =
_EQ001
=
Figure 5
shows a synthesized 4-bit equality comparator.
Figure 5. Synthesized 4-Bit Equality Comparator
The output pin
eq
is the output of the second LE of a cascade chain. The
LUT of
_LC2_B1
implements the comparison of the first two bits. The
comparison of the second two bits is implemented in the LUT of
_LC3_B1
.
The outputs of these two LUTs are then cascaded together to form the
output of
_LC3_B1
.
If
a2
and
eq
are both row I/O pins, the timing delay from
a2
to
eq
can be
estimated by adding the following microparameters:
t
IN
+ t
ROW
+
t
LOCAL
+
t
DATA_TO_OUT
+
t
ROW
+
t
LOCAL
+
t
OD1
a0
b0
a1
b1
_EQ002
LUT
a2
b2
a3
b3
LUT
eq
_EQ001C
_EQ002C
_LC3_B1
_LC2_B1
相关PDF资料 |
PDF描述 |
|---|---|
| EPF6016 | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| EPF6016A | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| EPF8025G | 10Base-T Interface Module with Enhanced Common Mode Attenuation |
| EPE6313SE | 10Base-T Interface Module with Enhanced Common Mode Attenuation |
| EPE6333G | 10Base-T Interface Module with Enhanced Common Mode Attenuation |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6024ABC256-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-3N | 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz CMOS Technology 3.3V 256-Pin BGA 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz 0.42um Technology 3.3V 256-Pin BGA |
发布紧急采购，3分钟左右您将得到回复。