参数资料
型号: EPF6024A
厂商: Altera Corporation
英文描述: Programmable Logic Device Family(FLEX6000可编程逻辑系列器件)
中文描述: 可编程逻辑器件系列(FLEX6000可编程逻辑系列器件)
文件页数: 8/21页
文件大小: 241K
代理商: EPF6024A
926
Altera Corporation
AN 92: Understanding FLEX 6000 Timing
t
OUTCO
Clock-to-output delay with global clock with LE
register using a FastFLEX
I/O pin. The delay from
when a rising edge is applied to the global clock pin
to the time the data appears at the FastFLEX I/O pin.
A FastFLEX I/O pin is a row or column output pin
that receives its data signals from the adjacent local
interconnect driven by an adjacent LE.
t
ODH
Output data hold time after clock. The minimum time
a registered output pin will remain at its previous
value after a rising edge is applied to the clock input
pin. This parameter applies for both global and non-
global clocking of LE registers.
FLEX 6000
Timing Model
Timing models are simplified block diagrams that illustrate the
propagation delays through Altera devices. Logic can be implemented
on different paths. You can trace the actual paths used in your device by
examining the equations listed in the MAX+PLUS II Report File (
.rpt
) for
the project. Add the appropriate internal timing parameters to calculate
the approximate propagation delays through the device. However, the
MAX+PLUS II Timing Analyzer provides the most accurate timing
information.
Figure 1
shows the FLEX 6000 timing model.
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