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参数资料
| 型号： | EPF6024A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 2/21页 |
| 文件大小： | 241K |
| 代理商： | EPF6024A |
920
Altera Corporation
AN 92: Understanding FLEX 6000 Timing
t
OD3
Output buffer and pad delay with the slow slew rate
logic option turned on.
t
XZ
Output buffer disable delay. The delay required for
high impedance to appear at the output pin after the
tri-state buffer’s enable control is disabled.
t
ZX1
Output buffer enable delay with the slow slew rate
logic option turned off and V
CCIO
= V
CCINT
. The delay
required for the output signal to appear at the output
pin after the tri-state buffer’s enable control is
enabled.
t
ZX2
Output buffer enable delay with the slow slew rate
logic option turned off and V
CCIO
= low voltage. The
delay required for the output signal to appear at the
output pin after the tri-state buffer’s enable control is
enabled.
t
ZX3
Output buffer enable delay with the slow slew rate
logic option turned on. The delay required for the
output signal to appear at the output pin after the
tri-state buffer’s enable control is enabled.
t
IOE
Output enable control delay. The delay for a signal
used to control the output enable of the IOE’s tri-state
buffer.
t
IN
Input pad and buffer to FastTrack
Interconnect
delay. The time required for a signal on an I/O pin,
used as an input, to reach a row or column channel of
the FastTrack Interconnect.
t
IN_DELAY
Input pad and buffer to FastTrack Interconnect delay
with additional delay turned on. The time required for
a signal on an I/O pin, used as an input, to reach a row
or column channel of the FastTrack Interconnect.
Interconnect Timing Microparameters
The following list describes the routing timing microparameters for the
FLEX 6000 device family:
t
LOCAL
Logic array block (LAB) local interconnect delay. The
delay incurred by a signal entering an LAB or by a
signal routed between logic elements (LEs) by local
routing.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6024ABC256-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024ABC256-3N | 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz CMOS Technology 3.3V 256-Pin BGA 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz 0.42um Technology 3.3V 256-Pin BGA |
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