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| 型号： | EPF6024AFC256-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA256 |
| 封装： | FINE LINE, BGA-256 |
| 文件页数： | 8/57页 |
| 文件大小： | 508K |
| 代理商： | EPF6024AFC256-2 |
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16
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Either the counter enable or the up/down control may be used for a given
counter. Moreover, the synchronous load can be used as a count enable by
routing the register output into the data input automatically when
requested by the designer.
The second LE of each LAB has a special function for counter mode; the
carry-in of the LE can be driven by a fast feedback path from the register.
This function gives a faster counter speed for counter carry chains starting
in the second LE of an LAB.
The Altera software implements functions to use the counter mode
automatically where appropriate. The designer does not have to decide
how the carry chain will be used.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the LAB-wide signals LABCTRL1 and LABCTRL2. The LE
register has an asynchronous clear that can implement an asynchronous
preset. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear
or preset. Because the clear and preset functions are active-low, the Altera
software automatically assigns a logic high to an unused clear or preset
signal. The clear and preset logic is implemented in either the
asynchronous clear or asynchronous preset mode, which is chosen during
design entry (see Figure 8).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6024AFC256-2AA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF6024AFC256-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 219 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024AFI256-2 | 功能描述:IC FLEX 6000 FPGA 24K 256-FBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:FLEX 6000 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| EPF6024AQC208-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6024AQC208-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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