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参数资料
| 型号： | EVAL-AD7322CBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/37页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7322 |
| 标准包装： | 1 |
| 系列： | iCMOS® |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行 |
| 输入范围： | ±10 V |
| 在以下条件下的电源（标准）： | 30mW @ 1MSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7322 |
| 已供物品： | 板，CD |
| 相关产品： | AD7322BRUZ-REEL-ND - IC ADC 12BIT+SAR 2CHAN 14-TSSOP AD7322BRUZ-REEL7-ND - IC ADC 12BIT+ SAR 2CHAN 14TSSOP AD7322BRUZ-ND - IC ADC 12BIT+ SAR 2CHAN 14TSSOP |
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AD7322
Data Sheet
Rev. B | Page 18 of 36
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7322.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7322 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7322 can operate
with either an internal or external reference. In Figure 32, the
AD7322 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The VCC pin can be connected to either a 3 V supply voltage or a
5 V supply voltage. VDD and VSS are the dual supplies for the
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see Table 6). The VDRIVE
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the VDRIVE input controls the voltage of
the serial interface. VDRIVE can be set to 3 V or 5 V.
AD7322
VCC
VDD1
SERIAL
INTERFACE
C/P
VIN0
VIN1
REFIN/OUT
CS
DOUT
VDRIVE
SCLK
DIN
DGND
10F
0.1F
+
10F
0.1F
+
10F
0.1F
+
ANALOG INPUTS
±10V, ±5V, ±2.5V
0V TO +10V
+15V
–15V
680nF
VSS1
VCC +2.7V TO +5.25V
1MINIMUM VDD AND VSS SUPPLY VOLTAGES
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
AGND
10F
0.1F
+
+3V SUPPLY
04863-
025
Figure 32. Typical Connection Diagram
ANALOG INPUT
Single-Ended Inputs
The AD7322 has a total of two analog inputs when operating in
single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
Figure 33 shows the configuration of the AD7322 in single-
ended mode.
AD73221
VIN0
V+
V–
VDD
VSS
VCC
5V
AGND
1ADDITIONAL PINS OMITTED FOR CLARITY.
04863-
026
Figure 33. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The AD7322 can have a total of one true differential analog
input pair. Differential signals have some benefits over single-
ended signals, including better noise immunity based on the
device’s common-mode rejection and improvements in
distortion performance. Figure 34 defines the configuration of
the true differential analog inputs of the AD7322.
04863-
027
AD73221
VIN+
VIN–
1ADDITIONAL PINS OMITTED FOR CLARITY.
NOTES
1. VIN+ REFERS TO VIN0 AND VIN– REFERS TO VIN1.
Figure 34. True Differential Inputs
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN inputs in
each differential pair (VIN+ VIN). VIN+ and VIN should
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 180° out of
phase. Assuming the ±4 × VREF mode, the amplitude of the
differential signal is 20 V to +20 V p-p (2 × 4 × VREF),
regardless of the common mode.
The common mode is the average of the two signals
(VIN+ + VIN)/2
and is therefore the voltage on which the two input signals
are centered.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common-mode range is
determined by the amplifier’s output swing. If the differential
inputs are not driven from an amplifier, the common-mode
range is determined by the supply voltage on the VDD supply pin
and the VSS supply pin.
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