参数资料
型号: EVAL-AD7322CBZ
厂商: Analog Devices Inc
文件页数: 35/37页
文件大小: 0K
描述: BOARD EVALUATION FOR AD7322
标准包装: 1
系列: iCMOS®
ADC 的数量: 1
位数: 12
采样率(每秒): 1M
数据接口: 串行
输入范围: ±10 V
在以下条件下的电源(标准): 30mW @ 1MSPS
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD7322
已供物品: 板,CD
相关产品: AD7322BRUZ-REEL-ND - IC ADC 12BIT+SAR 2CHAN 14-TSSOP
AD7322BRUZ-REEL7-ND - IC ADC 12BIT+ SAR 2CHAN 14TSSOP
AD7322BRUZ-ND - IC ADC 12BIT+ SAR 2CHAN 14TSSOP
AD7322
Data Sheet
Rev. B | Page 6 of 36
TIMING SPECIFICATIONS
Unless otherwise noted, VDD = 12 V to 16.5 V, VSS = 12 V to 16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25, VDRIVE ≤ VCC,
VREF = 2.5 V to 3.0 V internal/external, TA = TMAX to TMIN.1
Table 3.
Limit at TMIN, TMAX
Parameter
VCC < 4.75 V
VCC = 4.75 V to 5.25 V
Unit
Description
fSCLK
50
kHz min
14
20
MHz max
tCONVERT
16 × tSCLK
ns max
tSCLK = 1/fSCLK
tQUIET
75
60
ns min
Minimum time between end of serial read and next falling edge of CS
t1
12
5
ns min
Minimum CS pulse width
25
20
ns min
CS to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
45
35
ns min
Unipolar input range (0 V to 10 V)
t3
26
14
ns max
Delay from CS until DOUT three-state disabled
t4
57
43
ns max
Data access time after SCLK falling edge
t5
0.4 × tSCLK
ns min
SCLK low pulse width
t6
0.4 × tSCLK
ns min
SCLK high pulse width
t7
13
8
ns min
SCLK to data valid hold time
t8
40
22
ns max
SCLK falling edge to DOUT high impedance
10
9
ns min
SCLK falling edge to DOUT high impedance
t9
4
ns min
DIN setup time prior to SCLK falling edge
t10
2
ns min
DIN hold time after SCLK falling edge
tPOWER-UP
750
ns max
Power up from autostandby
500
s max
Power up from full shutdown/autoshutdown mode, internal reference
25
s typ
Power up from full shutdown/autoshutdown mode, external reference
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2
When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio must be limited to 50:50.
ZERO
1
2
3
4
5
13
14
15
16
WRITE
ZERO
REG
SEL
LSB
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t2
t6
t4
t9
t10
t3
t7
t5
t8
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ZERO
IDENTIFICATION BIT
04863-
002
DON’T
CARE
Figure 2. Serial Interface Timing Diagram
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