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| 型号： | EVAL-AD7730LEBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/53页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7730 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 600 |
| 数据接口： | 串行 |
| 输入范围： | ±80 mV |
| 在以下条件下的电源（标准）： | 125mW @ 600SPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7730 |
| 已供物品： | 板，CD |
| 相关产品： | AD7730LBRUZ-ND - IC ADC TRANSDUCER BRIDGE 24TSSOP AD7730LBRZ-ND - IC ADC TRANSDUCER BRIDGE 24SOIC AD7730LBRUZ-REEL7-ND - IC ADC TRANSDUCER BRIDGE 24TSSOP AD7730LBRZ-REEL-ND - IC ADC TRANSDUCER BRIDGE 24SOIC AD7730LBRUZ-REEL-ND - IC ADC TRANSDUCER BRIDGE 24TSSOP AD7730BRUZ-REEL7-ND - IC ADC BRIDGE TRANSDUCER 24TSSOP AD7730BRUZ-REEL-ND - IC ADC BRIDGE TRANSDUCER 24TSSOP AD7730BRUZ-ND - IC ADC TRANSDUCER BRIDGE 24TSSOP AD7730BNZ-ND - IC ADC TRANSDUCER BRIDGE 24-DIP AD7730BRZ-REEL7TR-ND - IC ADC BRDGE TRANSDCR 24SOIC TR 更多... |
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AD7730/AD7730L
–36–
In DSP applications, the SCLK is generally a continuous clock.
In these applications, the
CS input for the AD7730 is generated
from a frame synchronization signal from the DSP. In these
applications, the first edge after
CS goes low is the active edge.
The MSB of the data to be shifted into the DSP must be set up
prior to this first active edge. Unlike microcontroller applica-
tions, the DSP does not provide a clock edge to clock the MSB
from the AD7730. In this case, the
CS of the AD7730 places
the MSB on the DOUT line. For processors with the rising edge
of SCLK as the active edge, the POL input should be tied high.
In this case, the DSP takes data on the rising edge. If
CS goes
low while SCLK is low, the MSB is clocked out on the DOUT
line from the
CS. Subsequent data bits are clocked from the
falling edge of SCLK. For processors with the falling edge of
SCLK as the active edge, the POL input should be tied low. In
this case, the DSP takes data on the falling edge. If
CS goes low
while SCLK is high, the MSB is clocked out on the DOUT line
from the
CS. Subsequent data bits are clocked from the rising
edge of SCLK.
Figure 18. Read Cycle Timing Diagram
Figure 19. Write Cycle Timing Diagram
The
RDY line is used as a status signal to indicate when data is
ready to be read from the AD7730’s data register.
RDY goes
low when a new data word is available in the data register. It is
reset high when a read operation from the data register is com-
plete. It also goes high prior to the updating of the data register
to indicate when a read from the data register should not be
initiated. This is to ensure that the transfer of data from the data
register to the output shift register does not occur while the data
register is being updated. It is possible to read the same data
twice from the output register even though the
RDY line returns
high after the first read operation. Care must be taken, however,
to ensure that the read operations are not initiated as the next
output update is about to take place.
For systems with a single data line, the DIN and DOUT lines
on the AD7730 can be connected together, but care must be
taken in this case not to place the part in continuous read mode
as the part monitors DIN while supplying data on DOUT and
as a result, it may not be possible to take the part out of its
continuous read mode.
DOUT
SCLK
(POL = 1)
CS
RDY
MSB
t5
t7
t9
LSB
t8
t6
t4
t3
t10
SCLK
(POL = 0)
t5A
t6
t7
DIN
SCLK
(POL = 1)
CS
MSB
t12
t15
LSB
t16
t14
t11
t13
SCLK
(POL = 0)
t14
t15
REV. B
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