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参数资料
| 型号： | EVAL-AD7763EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/33页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL CONTROL AD7763 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 625k |
| 数据接口： | 并联 |
| 输入范围： | ±3.25 Vpp |
| 在以下条件下的电源（标准）： | 955.5mW @ 625kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7763 |
| 已供物品： | 板，CD |
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Data Sheet
AD7763
Rev. B | Page 19 of 32
CLOCKING THE AD7763
The AD7763 requires an external, low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal.
The ICLK controls the internal operations of the AD7763. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:
ICLK = MCLK (CDIV = 1)
ICLK = MCLK/2 (CDIV = 0)
This option is pin selectable (Pin 58). On power-up, the default
is ICLK = MCLK/2 to ensure that the part can handle the maxi-
mum MCLK frequency of 40 MHz. For output data rates equal to
those used in audio systems, a 12.288 MHz ICLK frequency can
be used. As shown in Table 6, output data rates of 192 kHz, 96 kHz,
and 48 kHz are achievable with this ICLK frequency. As mentioned
previously, this ICLK frequency can be derived from different
MCLK frequencies.
The MCLK jitter requirements depend on a number of factors
and are determined by
20
)
dB
(
)
(
10
2
SNR
IN
rms
j
f
OSR
t
×
π
×
=
Where:
OSR = oversampling ratio =
ODR
fICLK .
fIN = maximum input frequency.
SNR(dB) = target SNR.
EXAMPLE 1
This example is taken from Table 6, where:
ODR = 625 kHz.
fICLK = 20 MHz.
fIN (maximum) = 250 kHz.
SNR = 108 dB.
ps
6
.
3
10
250
2
32
6
3
)
(
=
×
=
π
rms
j
t
This is the maximum allowable clock jitter for a full-scale,
250 kHz input tone with the given ICLK and output data rate.
EXAMPLE 2
Following is a second example from Table 6, where:
ODR = 48 kHz.
fICLK = 12.288 MHz.
fIN (maximum) = 19.2 kHz.
SNR = 120 dB.
ps
133
10
2
.
19
2
256
6
3
)
(
=
×
π
×
=
rms
j
t
The input amplitude also has an effect on these jitter figures.
If, for example, the input level is 3 dB below full scale, the allowable
jitter is increased by a factor of √2, increasing the first example
to 2.53 ps rms. This happens when the maximum slew rate is
decreased by a reduction in amplitude. Figure 29 and Figure 30
illustrate this point, showing the maximum slew rate of a sine
wave of the same frequency but with different amplitudes.
1.0
–1.0
05476-
014
0.5
0
–0.5
Figure 29. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p
1.0
–1.0
05476-
015
0.5
0
–0.5
Figure 30. Maximum Slew Rate of Same Frequency Sine Wave
with Amplitude of 1 V p-p
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