参数资料
| 型号： | EVAL-ADV7195EB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7195 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7195 |
| 主要属性： | 多格式顺序扫描/HDTV 编码器，3 个 11 位 ADC |
| 次要属性： | 内部测试样式发生器，带颜色控制 |
| 已供物品： | 板 |
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ADV7195
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)
Figure 23 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
HDTV Enable (MR30)
When this bit is set to “1,” the ADV7195 reverts to HDTV mode
(refer to HDTV mode section). When set to “0” the ADV7195
is set up in Progressive Scan Mode (PS Mode).
Reserved (MR31–MR32)
A “0” must be written to these bits.
DAC A Control (MR33)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)
Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
DAC C Control (MR35)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
Interpolation (MR36)
This bit enables the second stage interpolation filters. When this
bit is enabled (MR36 = “1”), data is sent at 54 MHz to the DAC
output stage. After Reset it is recommended to toggle this bit.
Before toggling this bit, 3Ehex must be written to address 09hex
to guarantee correct operation.
Reserved (MR37)
A “0” must be written to this bit.
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Figure 24 shows the various operations under the control of
Mode Register 4.
MR4 BIT DESCRIPTION
Timing Reset (MR40)
Toggling MR40 from low to high and low again resets the inter-
nal horizontal and vertical timing counters.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4-SR0) = 05H)
Figure 25 shows the various operations under the control of
Mode Register 5.
MR5 BIT DESCRIPTION
Reserved (MR50)
This bit is reserved for the revision code.
RGB Mode (MR51)
When RGB mode is enabled (MR51 = “1”) the ADV7195
accepts unsigned binary RGB data at its input port. This control
is also available in Async Timing Mode.
Sync on PrPb (MR52)
By default, the color component output signals Pr, Pb do not
contain any horizontal sync pulses. They can be inserted when
MR52 = “1.” This facility is only available when Output Stan-
dard Selection has been set to EIA-770.2 (MR01–00 = “00”) or
Full Input Range (MR01–00 = “10”).
This control is not available in RGB mode.
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR37
ZERO MUST BE
WRITTEN TO
THIS BIT
DAC B CONTROL
MR34
0 POWER-DOWN
1 NORMAL
MR32
ZERO MUST BE
WRITTEN TO
THIS BIT
HDTV ENABLE
MR30
0 DISABLE
1 ENABLE
INTERPOLATION
MR36
0 DISABLE
1 ENABLE
DAC C CONTROL
MR35
0 POWER-DOWN
1 NORMAL
DAC A CONTROL
MR33
0 POWER-DOWN
1 NORMAL
MR31
ZERO MUST BE
WRITTEN TO
THIS BIT
Figure 23. Mode Register 3
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
MR47 – MR41
ZERO MUST BE
WRITTEN TO
THESE BITS
Figure 24. Mode Register 4
–18 –
TIMING RESET
MR40
REV. A
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