参数资料
| 型号： | EVAL-ADV7195EB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7195 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7195 |
| 主要属性： | 多格式顺序扫描/HDTV 编码器，3 个 11 位 ADC |
| 次要属性： | 内部测试样式发生器，带颜色控制 |
| 已供物品： | 板 |
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ADV7195
3.3 V TIMING–SPECIFICATIONS
(V AA = 3.15 V to 3.45 V, V REF = 1.235 V, R SET = 2470
T MIN to T MAX [0 C to 70 C] unless otherwise noted.)
, R LOAD = 300
. All specifications
P arameter
Min
Typ
Max
Unit
Conditions
MPU PORT
1
SCLOCK Frequency
0
400
kHz
SCLOCK High Pulsewidth, t 1
SCLOCK Low Pulsewidth, t 2
Hold Time (Start Condition), t 3
Setup Time (Start Condition), t 4
Data Setup Time, t 5
SDATA, SCLOCK Rise Time, t 6
0.6
1.3
0.6
0.6
100
300
μ s
μ s
μ s
μ s
ns
ns
After this Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
SDATA, SCLOCK Fall Time, t 7
Setup Time (Stop Condition), t 8
RESET Low Time
0.6
100
300
ns
μ s
ns
ANALOG OUTPUTS
Analog Output Delay, t 62
Analog Output Skew
CLOCK CONTROL AND PIXEL PORT 3
10
0.5
ns
ns
f CLK
27
74.25
81
MHz
MHz
MHz
Progressive Scan Mode
HDTV Mode
ASYNC Timing Mode and 1 × Interpolation
Clock High Time, t 9
Clock Low Time, t 10
Data Setup Time, t 11
Data Hold Time, t 12
Control Setup Time, t 11
5.0
5.0
2.0
4.5
7.0
21.5
22.0
3.4
3.2
3.4
ns
ns
ns
ns
ns
Control Hold Time, t 12
Pipeline Delay
Pipeline Delay
4.0
16
29
3.2
ns
Clock Cycles
Clock Cycles
For 4:4:4 Pixel Input Format at 1 × Oversampling
For 4:4:4 or 4:2:2 Pixel Input Format at
2 × Oversampling
NOTES
1
2
3
Guaranteed by characterization.
Output delay measured from 50% point of rising edge of CLOCK to the 50% point of DAC output full-scale transition.
Data: Cb/Cr(9–0), Cr(9–0), Y(9–0); Control: HSYNC / SYNC , VSYNC /TSYNC, DV.
Specifications subject to change without notice.
REV. A
–5 –
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